ZHCSCE6 April   2014 DRV8824-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Motor Drivers
      2. 8.3.2 Current Regulation
      3. 8.3.3 Blanking Time
      4. 8.3.4 Microstepping Indexer
      5. 8.3.5 nRESET, nENBLE and nSLEEP Operation
      6. 8.3.6 Protection Circuits
        1. 8.3.6.1 Overcurrent Protection (OCP)
        2. 8.3.6.2 Thermal Shutdown (TSD)
        3. 8.3.6.3 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Information
        1. 8.3.7.1 Thermal Protection
        2. 8.3.7.2 Power Dissipation
        3. 8.3.7.3 Heatsinking
    4. 8.4 Device Functional Modes
      1. 8.4.1 Decay Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stepper Motor Speed
        2. 9.2.2.2 Current Regulation
        3. 9.2.2.3 Decay Modes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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10 Power Supply Recommendations

The DRV8824-Q1 is designed to operate from an input voltage supply (VM) range between 8.2 V and 45 V. Two 0.01-µF ceramic capacitorS rated for VMA and VMB must be placed as close to the DRV8824-Q1 as possible. In addition, a bulk capacitor must be included. If VMA and VMB are connected to the same board net, a single bulk capacitor is sufficient.