ZHCSQZ4A July   2022  – October 2022 DRV8300U

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 Gate Drive Timings
          1. 8.3.1.1.1 Propagation Delay
          2. 8.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 8.3.1.2 Mode (Inverting and non inverting INLx)
      2. 8.3.2 Pin Diagrams
      3. 8.3.3 Gate Driver Protective Circuits
        1. 8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

8.7 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (GVDD, BSTx)
IGVDDGVDD standby mode current INHx = INLX = 0; VBSTx = VGVDD4008001400µA
GVDD active mode current INHx = INLX = Switching @20kHz; VBSTx = VGVDD; NO FETs connected4008251400µA
ILBSxBootstrap pin leakage currentVBSTx = VSHx = 85V; VGVDD = 0V247µA
ILBS_TRANBootstrap pin active mode transient leakage current INHx = Switching@20kHz30105220µA
ILBS_DCBootstrap pin active mode leakage static current INHx = High3085150µA
ILSHxHigh-side source pin leakage current INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V305580µA
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL_MODEInput logic low voltageMode pin0.6V
VILInput logic low voltageINLx, INHx pins0.8V
VIH_MODEInput logic high voltageMode pin3.7V
VIHInput logic high voltageINLx, INHx pins2.0V
VHYS_MODEInput hysteresisMode pin160020002400mV
VHYSInput hysteresisINLx, INHx pins40100260mV
IIL_INLxINLx Input logic low currentVPIN (Pin Voltage) = 0 V; INLx in non-inverting mode-101µA
VPIN (Pin Voltage) = 0 V; INLx in inverting mode52030µA
IIH_INLxINLx Input logic high currentVPIN (Pin Voltage) = 5 V; INLx in non-inverting mode52030µA
VPIN (Pin Voltage) = 5 V; INLx in inverting mode00.51.5µA
IILINHx, MODE Input logic low currentVPIN (Pin Voltage) = 0 V; -101µA
IIHINHx, MODE Input logic high currentVPIN (Pin Voltage) = 5 V; 52030µA
RPD_INHxINHx Input pulldown resistanceTo GND120200280kΩ
RPD_INLxINLx Input pulldown resistanceTo GND, INLx in non-inverting mode120200280kΩ
RPU_INLxINLx Input pullup resistanceTo INT_5V, INLx in inverting mode120200280kΩ
RPD_MODEMODE Input pulldown resistanceTo GND120200280kΩ
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGHx_LOHigh-side gate drive low level voltageIGLx = -100 mA; VGVDD = 12V; No FETs connected00.150.35V
VGHx_HIHigh-side gate drive high level voltage (VBSTx - VGHx)IGHx = 100 mA; VGVDD = 12V; No FETs connected0.30.61.2V
VGLx_LOLow-side gate drive low level voltageIGLx = -100 mA; VGVDD = 12V; No FETs connected00.150.35V
VGLx_HILow-side gate drive high level voltage (VGVDD - VGHx)IGHx = 100 mA; VGVDD = 12V; No FETs connected0.30.61.2V
IDRIVEP_HSHigh-side peak source gate currentGHx-SHx = 12V 4007501200mA
IDRIVEN_HSHigh-side peak sink gate currentGHx-SHx = 0V 85015002100mA
IDRIVEP_LSLow-side peak source gate currentGLx = 12V 4007501200mA
IDRIVEN_LSLow-side peak sink gate currentGLx = 0V 85015002100mA
tPDInput to output propagation delayINHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx70125180ns
tPD_matchMatching propagation delay per phaseGHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx-30±430ns
tPD_matchMatching propagation delay phase to phaseGHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx-30±430ns
tR_GLxGLx rise time (10% to 90%)CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V102450ns
tR_GHxGHx rise time (10% to 90%)CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V102450ns
tF_GLxGLx fall time (90% to 10%)CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V51230ns
tF_GHxGHx fall time (90% to 10%)CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V51230ns
tDEADGate drive dead timeDT pin floating150215280ns
DT pin connected to GND150215280ns
40 kΩ between DT pin and GND150200260ns
400 kΩ between DT pin and GND150020002600ns
tPW_MINMinimum input pulse width on INHx, INLx that changes the output on GHx, GLx4070150ns
BOOTSTRAP DIODES(DRV8300UD, DRV8300UDI)
VBOOTDBootstrap diode forward voltageIBOOT = 100 µA0.450.70.85V
IBOOT = 100 mA22.33.1V
RBOOTDBootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT)IBOOT = 100 mA and 80 mA111525Ω
PROTECTION CIRCUITS
VGVDDUVGate Driver Supply undervoltage lockout (GVDDUV)Supply rising88.38.6V
Supply falling7.888.25V
VGVDDUV_HYSGate Driver Supply UV hysteresisRising to falling threshold295330360mV
tGVDDUVGate Driver Supply undervoltage deglitch time51013µs
VBSTUVBoot Strap undervoltage lockout (VBSTx - VSHx)Supply rising7.588.7V
Boot Strap undervoltage lockout (VBSTx - VSHx)Supply falling6.97.68.4V
VBSTUV_HYSBootstrap UV hysteresisRising to falling threshold250400850mV
tBSTUVBootstrap undervoltage deglitch time5.51022µs