ZHCSDJ3C March   2015  – June 2019 DLPC150

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      DLP 0.2 英寸 WVGA 芯片组
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 DLPC150 Mechanical Data
      1. Table 1. I/O Type Subscript Definition
      2. Table 2. Internal Pullup and Pulldown Characteristics
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Host_irq Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Parallel Interface Supports Two Data Transfer Formats
        1. 7.2.1.1 Pdata Bus – Parallel Interface Bit Mapping Modes
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Interface Timing Requirements
        1. 8.3.1.1 Parallel Interface
      2. 8.3.2 Serial Flash Interface
      3. 8.3.3 Serial Flash Programming
      4. 8.3.4 I2C Control Interface
      5. 8.3.5 DMD (Sub-LVDS) Interface
      6. 8.3.6 Calibration And Debug Support
      7. 8.3.7 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC150 System Design Consideration – Application Notes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC150 System Interfaces
          1. 9.2.2.1.1 Control Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC150 Power-Up Initialization Sequence
    3. 10.3 DMD Fast Park Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines For Internal Controller PLL Power
      2. 11.1.2 DLPC150 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
        1. 12.1.1.1 器件标记
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13"机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

8.3.5 DMD (Sub-LVDS) Interface

The DLPC150 controller DMD interface consists of a high speed 1.8-V sub-LVDS output only interface with a maximum clock speed of 532-MHz DDR and a low speed SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. The DLPC150 sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the DLPC150 also supports a limited number of DMD interface swap configurations that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 9 shows the four options available for the DLP2010 or DLP2010NIR (0.2-inch WVGA) DMD. Any unused DMD signal pairs should be left unconnected on the final board design.

Table 9. DLP2010 or DLP2010NIR (0.2-Inch WVGA) DMD – Controller to 4-Lane DMD Pin Mapping Options

DLPC150 CONTROLLER 4 LANE DMD ROUTING OPTIONS DMD PINS
OPTION 1
SWAP CONTROL = x0		 OPTION 2
SWAP CONTROl = x2		 OPTION 3
SWAP CONTROL = x1		 OPTION 4
SWAP CONTROL = x3
HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_H_P
HS_WDATA_H_N		 HS_WDATA_A_P
HS_WDATA_A_N		 Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_G_P
HS_WDATA_G_N		 HS_WDATA_B_P
HS_WDATA_B_N		 Input DATA_p_1
Input DATA_n_1
HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_B_P
HS_WDATA_B_N		 HS_WDATA_G_P
HS_WDATA_G_N		 Input DATA_p_2
Input DATA_n_2
HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_A_P
HS_WDATA_A_N		 HS_WDATA_H_P
HS_WDATA_H_N		 Input DATA_p_3
Input DATA_n_3
DLPC150 DMD subLVDS.gifFigure 11. DLP2010 Or DLP2010NIR (0.2-Inch WVGA) DMD Interface Example (Mapping Option 1 Shown)