ZHCSHA4B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.11 1.8 V to 5.5 V Logic Interface

All digital input and output pins are compatible with any logic supply voltage between 1.8 V and 5.5 V. Connect the interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7 V (see the Timing Characteristics), IOVDD can operate as low as 1.8 V, but with degraded timing and temperature performance. For the lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND. Note that the DAC8881 core internal digital logic operates from the same voltage as the 2.7V to 5.5V AVDD supply, so the DVDD pin must also be connected to the AVDD supply voltage.