ZHCSEV4A February 2016 – March 2016 DAC8551-Q1
PRODUCTION DATA.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Applications
8.2.1 Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116
Figure 32. Loop-Powered Transmitter
8.2.1.1 Design Requirements
This design is commonly referred to as a loop-powered, or 2-wire, 4 mA to 20 mA transmitter. The transmitter has only two external input terminals: a supply connection and an output, or return, connection. The transmitter communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its return current. In order to conform to the 4 mA to 20 mA communication standard, the complete transmitter must consume less than 4 mA of current. The DAC8551-Q1 enables the accurate control of the loop current from 4 mA to 20 mA in 16-bit steps.
8.2.1.2 Detailed Design Procedure
Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides simplicity and improved performance due to the matched internal resistors. The output current can be modified if necessary by looking using Equation 2.
For more details of this application, see 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7). It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.
8.2.2 Bipolar Operation Using the DAC8551-Q1
The DAC8551-Q1 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 35. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
Figure 35. Bipolar Output Range
The output voltage for any input code can be calculated as follows:
where D represents the input code in decimal (0–65 535)
with VREF = 5V, R1 = R2 = 10 kΩ.
Using this example, an output voltage range of ±5 V with 0000h corresponding to a –5 V output and FFFFh corresponding to a 5 V output can be achieved. Similarly, using VREF = 2.5 V, a ±2.5 V output voltage range can be achieved.
8.2.3 Using the REF02 As a Power Supply for the DAC8551-Q1
Due to the extremely low supply current required by the DAC8551-Q1, an alternative option is to use a precision reference such as the REF02 device to supply the required voltage to the device, as illustrated in Figure 36.
Figure 36. REF02 As a Power Supply to the DAC8551-Q1
This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 device outputs a steady supply voltage for the DAC8551-Q1. If the REF02 device is used, the current it must supply to the DAC8551-Q1 is 200 μA. This configuration is with no load on the output of the DAC. When a DAC output is loaded, the REF02 also must supply the current to the load.
The total current required (with a 5 kΩ load on the DAC output) is:
The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2 mA current drawn from it. This value corresponds to a 3.9 LSB error.
8.3 System Examples
8.3.1 Interface from DAC8551-Q1 to 8051
See Figure 37 for a serial interface between the DAC8551-Q1 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8551-Q1, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data are to be transmitted to the DAC8551-Q1, P3.3 is taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DAC8551-Q1 requires data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and mirror the data as needed.
Figure 37. Interface from DAC8551-Q1 Devices to 80C51 or 80L51
8.3.2 Interface from DAC8551-Q1 to Microwire
Figure 38 shows an interface between the DAC8551-Q1 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and is clocked into the DAC8551-Q1 on the rising edge of the SK signal.
Figure 38. Interface from DAC8551-Q1 Devices to Microwire
8.3.3 Interface from DAC8551-Q1 to 68HC11
Figure 39 shows a serial interface between the DAC8551-Q1 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8551-Q1, whereas the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
Figure 39. Interface from DAC8551-Q1 Devices to 68HC11
The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DAC88551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write operation are performed to the DAC. PC7 is taken high at the end of this procedure.