ZHCSRX2 march   2023 DAC53004W

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 规格
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 详细说明
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 特性说明
      1. 7.3.1 智能数模转换器 (DAC) 架构
      2. 7.3.2 数字输入/输出
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 器件功能模式
      1. 7.4.1 电压输出模式
        1. 7.4.1.1 电压基准和 DAC 传递函数
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 比较器模式
        1. 7.4.3.1 可编程迟滞比较器
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 故障转储模式
      5. 7.4.5 应用特定模式
        1. 7.4.5.1 电压裕量和调节
          1. 7.4.5.1.1 高阻抗输出和 PROTECT 输入
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 函数生成
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 器件复位和故障管理
        1. 7.4.6.1 上电复位 (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM 循环冗余校验 (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER 位
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT 位
      7. 7.4.7 Power-Down Mode
    5. 7.5 编程
      1. 7.5.1 SPI 编程模式
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S 模式协议
        2. 7.5.2.2 I2C 更新序列
          1. 7.5.2.2.1 地址字节
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C 读取序列
      3. 7.5.3 通用输入/输出 (GPIO) 模式
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS 寄存器（地址 = 23h）[复位 = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      20. 7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      21. 7.6.21 PMBUS-PAGE Register [reset = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
      23. 7.6.23 PMBUS-CML Register [reset = 0000h]
      24. 7.6.24 PMBUS-VERSION 寄存器 [复位 = 2200h]
  8. 8 应用和实现
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 布局
      1. 8.4.1 布局指南
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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6.6 Electrical Characteristics: Current Output

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V, ±250-µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 8 Bits
INL Integral nonlinearity DAC codes between 10d and 255d for current output range of 0 µA to 25 µA, DAC codes between 0d and 255d for other ranges –1 1 LSB
DNL Differential nonlinearity DAC codes between 10d and 255d for current output range of 0 µA to 25 µA, DAC codes between 0d and 255d for other ranges –1 1 LSB
Offset error DAC output range: 0 µA to 25 µA, DAC at code 10d ±1.5 %FSR
Offset error DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; DAC at zero-scale 5 %FSR
Offset error all unipolar negative ranges, DAC at zero-scale -5 %FSR
Offset error DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; DAC at midscale ±1 %FSR
Gain error DAC output range: 0 µA to 25 µA, DAC codes between 10d and 255d ±1.5 %FSR
Gain error DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; DAC codes between 0d and 255d ±1.5 %FSR
Gain error all unipolar negative ranges, DAC codes between 0d and 255d ±5 %FSR
Gain error DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; DAC codes between 0d and 255d ±1.3 %FSR
OUTPUT
Output compliance voltage(1) DAC output range: 0 µA to 25 µA, to VDD and to AGND 200 mV
Output compliance voltage(1) DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; to VDD 400 mV
Output compliance voltage(1) all unipolar negative ranges, to VDD 400 mv
Output compliance voltage(1) DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; to VDD and to AGND 400 mV
ZO IOUT dc output impedance(2) DAC at midscale, DAC output kept at VDD/2 60 MΩ
Power supply rejection ratio (dc) DAC at midscale, output range: 0 µA to 25 µA, VDD changed from 4.5 V to 5.5 V 0.28 LSB/V
Power supply rejection ratio (dc) DAC at midscale, all unipolar positive ranges, VDD changed from 4.5 V to 5.5V 0.33 LSB/V
Power supply rejection ratio (dc) DAC at midscale, all unipolar negative ranges, VDD changed from 4.5 V to 5.5V 0.83 LSB/V
Power supply rejection ratio (dc) DAC at midscale, all bipolar ranges, VDD changed from 4.5V to 5.5V 0.23 LSB/V
DYNAMIC PERFORMANCE
tsett Output current settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB at 8-bit resolution, VDD = 5.5 V, common-mode voltage at OUTx pin is VDD/2 60 µs
Vn Output noise current (peak to peak) 0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range		 150 nAPP
Output noise density f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range		 1 nA/√Hz
Power supply rejection ratio (ac)(3) ±250 µA output range, 200-mV 50-Hz or 60-Hz sine wave superimposed on power-supply voltage, DAC at midscale 0.65 LSB/V
POWER
IDD Current flowing into VDD(3) (4) Normal operation, DACs at midscale, all unipolar output ranges, digital pins static 18 24 µA/ch
IDD Current flowing into VDD(3) (4) Normal operation, DACs at full scale, ±25-µA output range, digital pins static 42 50 µA/ch
Normal operation, DACs at full scale, ±50-µA output range, digital pins static 56 70
Normal operation, DACs at full scale, ±125-µA output range, digital pins static 98 120
Normal operation, DACs at full scale, ±250-µA output range, digital pins static 167 200
(1) Measured between DAC codes 0d and 255d.
(2) Specified by design and characterization, not production tested.
(3) The current flowing into VDD does not account for the load current sourced or sunk on the OUTx pins. The VREF pin is connected to VDD.
(4) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).