SNAS265J June   2005  – September 2015 DAC121S101 , DAC121S101-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description continued
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DSP and Microprocessor Interfacing
        1. 9.1.1.1 ADSP-2101/ADSP2103 Interfacing
          1. 9.1.1.1.1 80C51/80L51 Interface
          2. 9.1.1.1.2 68HC11 Interface
          3. 9.1.1.1.3 Microwire Interface
      2. 9.1.2 Bipolar Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Specification Definitions
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply Voltage, VA 6.5 V
Voltage on any Input Pin −0.3 (VA + 0.3) V
Input Current at Any Pin (3) 10 mA
Package Input Current (3) 20 mA
Power Consumption at TA = 25°C See (4)
Soldering Temperature, Infrared, 10 Seconds(5) 235 °C
Storage Temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Machine Model ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN NOM MAX UNIT
Operating Temperature Range DAC121S101 −40 TA 105 °C
DAC121S101-Q1 −40 TA 125 °C
Supply Voltage, VA 2.7 5.5 V
Any Input Voltage(6) −0.1 (VA + 0.1) V
Output Load 0 1500 pF
SCLK Frequency 30 MHz

7.4 Thermal Information

THERMAL METRIC(1) DAC121S101, DAC121S101-Q1 UNIT
DGK (VSSOP) DDC (SOT)
8 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 240 250 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(7) TYP(7) MAX(7) UNIT
STATIC PERFORMANCE
Resolution TMIN ≤ TA ≤ TMAX 12 Bits
Monotonicity TMIN ≤ TA ≤ TMAX 12 Bits
INL Integral Non-Linearity Over Decimal codes 48 to 4047 TA = 25°C ±2.6 LSB
TMIN ≤ TA ≤ TMAX ±8
DNL Differential Non-Linearity VA = 2.7 V to 5.5 V TA = 25°C −0.15 +0.25 LSB
TMIN ≤ TA ≤ TMAX −0.7 +1 LSB
VA = 4.5 V to 5.5 V (8) TA = 25°C ±0.11 LSB
TMIN ≤ TA ≤ TMAX ±0.5
ZE Zero Code Error IOUT = 0 TA = 25°C +4 mV
TMIN ≤ TA ≤ TMAX +15
FSE Full-Scale Error IOUT = 0 TA = 25°C −0.06 %FSR
TMIN ≤ TA ≤ TMAX −1
GE Gain Error All ones Loaded to DAC register TA = 25°C −0.1 %FSR
TMIN ≤ TA ≤ TMAX ±1
ZCED Zero Code Error Drift −20 µV/°C
TC GE Gain Error Tempco VA = 3 V −0.7 ppm/°C
VA = 5 V −1 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range(8) TMIN ≤ TA ≤ TMAX 0 VA V
ZCO Zero Code Output VA = 3 V, IOUT = 10 µA 1.8 mV
VA = 3 V, IOUT = 100 µA 5 mV
VA = 5 V, IOUT = 10 µA 3.7 mV
VA = 5 V, IOUT = 100 µA 5.4 mV
FSO Full Scale Output VA = 3 V, IOUT = 10 µA 2.997 V
VA = 3 V, IOUT = 100 µA 2.99 V
VA = 5 V, IOUT = 10 µA 4.995 V
VA = 5 V, IOUT = 100 µA 4.992 V
Maximum Load Capacitance RL = ∞ 1500 pF
RL = 2 kΩ 1500 pF
DC Output Impedance 1.3 Ohm
IOS Output Short Circuit Current VA = 5 V, VOUT = 0 V,
Input code = FFFh
−63 mA
VA = 3 V, VOUT = 0 V,
Input code = FFFh
−50 mA
VA = 5 V, VOUT = 5 V,
Input code = 000h
74 mA
VA = 3 V, VOUT = 3 V,
Input code = 000h
53 mA
LOGIC INPUT
IIN Input Current (8) TMIN ≤ TA ≤ TMAX ±1 µA
VIL Input Low Voltage (8) VA = 5 V
TMIN ≤ TA ≤ TMAX
0.8 V
VA = 3 V
TMIN ≤ TA ≤ TMAX
0.5 V
VIH Input High Voltage (8) VA = 5 V
TMIN ≤ TA ≤ TMAX
2.4 V
VA = 3 V
TMIN ≤ TA ≤ TMAX
2.1 V
CIN Input Capacitance (8) TMIN ≤ TA ≤ TMAX 3 pF
POWER REQUIREMENTS
IA Supply Current (output unloaded) Normal Mode
fSCLK = 30 MHz
VA = 5.5 V TA = 25°C 260 µA
TMIN ≤ TA ≤ TMAX 312
VA = 3.6 V TA = 25°C 177 µA
TMIN ≤ TA ≤ TMAX 217
Normal Mode
fSCLK = 20 MHz
VA = 5.5 V TA = 25°C 224 µA
TMIN ≤ TA ≤ TMAX 279
VA = 3.6 V TA = 25°C 158 µA
TMIN ≤ TA ≤ TMAX 197
Normal Mode
fSCLK = 0
VA = 5.5 V 153 µA
VA = 3.6 V 118 µA
All PD Modes,
fSCLK = 30 MHz
VA = 5 V 84 µA
VA = 3 V 42 µA
All PD Modes,
fSCLK = 20 MHz
VA = 5 V 56 µA
VA = 3 V 28 µA
All PD Modes,
fSCLK = 0 (8)
VA = 5.5 V TA = 25°C 0.07 µA
TMIN ≤ TA ≤ TMAX 1
VA = 3.6 V TA = 25°C 0.04 µA
TMIN ≤ TA ≤ TMAX 1
PC Power Consumption (output unloaded) Normal Mode
fSCLK = 30 MHz
VA = 5.5 V TA = 25°C 1.43 mW
TMIN ≤ TA ≤ TMAX 1.72
VA = 3.6 V TA = 25°C 0.64 mW
TMIN ≤ TA ≤ TMAX 0.78
Normal Mode
fSCLK = 20 MHz
VA = 5.5 V TA = 25°C 1.23 mW
TMIN ≤ TA ≤ TMAX 1.53
VA = 3.6 V TA = 25°C 0.57 mW
TMIN ≤ TA ≤ TMAX 0.71
Normal Mode
fSCLK = 0
VA = 5.5 V 0.84 µW
VA = 3.6 V 0.42 µW
All PD Modes,
fSCLK = 30 MHz
VA = 5 V 0.42 µW
VA = 3 V 0.13 µW
All PD Modes,
fSCLK = 20 MHz
VA = 5 V 0.28 µW
VA = 3 V 0.08 µW
All PD Modes,
fSCLK = 0 (8)
VA = 5.5 V TA = 25°C 0.39 µW
TMIN ≤ TA ≤ TMAX 5.5
VA = 3.6 V TA = 25°C 0.14 µW
TMIN ≤ TA ≤ TMAX 3.6
IOUT / IA Power Efficiency ILOAD = 2 mA VA = 5 V 91%
VA = 3 V 94%

7.6 AC and Timing Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLK SCLK Frequency TMIN ≤ TA ≤ TMAX 30 MHz
ts Output Voltage Settling Time (8) 400h to C00h code change, RL = 2 kΩ CL ≤ 200 pF TA = 25°C 8 µs
TMIN ≤ TA ≤ TMAX 10
CL = 500 pF 12 µs
00Fh to FF0h code change, RL = 2 kΩ CL ≤ 200 pF 8 µs
CL = 500 pF 12 µs
SR Output Slew Rate 1 V/µs
Glitch Impulse Code change from 800h to 7FFh 12 nV-s
Digital Feedthrough 0.5 nV-s
tWU Wake-Up Time VA = 5 V 6 µs
VA = 3 V 39 µs
1/fSCLK SCLK Cycle Time TMIN ≤ TA ≤ TMAX 33 ns
tH SCLK High time TA = 25°C 5 ns
TMIN ≤ TA ≤ TMAX 13
tL SCLK Low Time TA = 25°C 5 ns
TMIN ≤ TA ≤ TMAX 13
tSUCL Set-up Time SYNC to SCLK Rising Edge TA = 25°C −15 ns
TMIN ≤ TA ≤ TMAX 0
tSUD Data Set-up Time TA = 25°C 2.5 ns
TMIN ≤ TA ≤ TMAX 5
tDHD Data Hold Time TA = 25°C 2.5 ns
TMIN ≤ TA ≤ TMAX 4.5
tCS SCLK fall to rise of SYNC VA = 5 V TA = 25°C 0 ns
TMIN ≤ TA ≤ TMAX 3
VA = 3 V TA = 25°C –2 ns
TMIN ≤ TA ≤ TMAX 1
tSYNC SYNC High Time 2.7 ≤ VA ≤ 3.6 TA = 25°C 9 ns
TMIN ≤ TA ≤ TMAX 20
3.6 ≤ VA ≤ 5.5 TA = 25°C 5 ns
TMIN ≤ TA ≤ TMAX 10
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified
(3) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by TJMAX, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must always be avoided.
(5) See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices.
(6) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.
DAC121S101 DAC121S101-Q1 20114904.gif
(7) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(8) This parameter is specified by design and/or characterization and is not tested in production.
DAC121S101 DAC121S101-Q1 20114905.gif Figure 1. Input / Output Transfer Characteristic
DAC121S101 DAC121S101-Q1 20114906.gif Figure 2. DAC121S101 Timing

7.7 Typical Characteristics

fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated
DAC121S101 DAC121S101-Q1 20114952.png Figure 3. DNL at VA = 3 V
DAC121S101 DAC121S101-Q1 20114954.png Figure 5. INL at VA = 3 V
DAC121S101 DAC121S101-Q1 20114956.png Figure 7. TUE at VA = 3 V
DAC121S101 DAC121S101-Q1 20114922.png Figure 9. DNL vs. VA
DAC121S101 DAC121S101-Q1 20114950.png Figure 11. 3-V DNL vs. fSCLK
DAC121S101 DAC121S101-Q1 20114924.png Figure 13. 3-V DNL vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114926.png Figure 15. 3-V DNL vs. Temperature
DAC121S101 DAC121S101-Q1 20114929.png Figure 17. 5-V INL vs. fSCLK
DAC121S101 DAC121S101-Q1 20114931.png Figure 19. 5-V INL vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114933.png Figure 21. 5-V INL vs. Temperature
DAC121S101 DAC121S101-Q1 20114935.png Figure 23. Zero Code Error vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114937.png Figure 25. Full-Scale Error vs. fSCLK
DAC121S101 DAC121S101-Q1 20114939.png Figure 27. Full-Scale Error vs. Temperature
DAC121S101 DAC121S101-Q1 20114945.png Figure 29. Supply Current vs. Temperature
DAC121S101 DAC121S101-Q1 20114947.png Figure 31. Power-On Reset
DAC121S101 DAC121S101-Q1 20114949.png Figure 33. 5-V Wake-Up Time
DAC121S101 DAC121S101-Q1 20114953.png Figure 4. DNL at VA = 5 V
DAC121S101 DAC121S101-Q1 20114955.png Figure 6. INL at VA = 5 V
DAC121S101 DAC121S101-Q1 20114957.png Figure 8. TUE at VA = 5 V
DAC121S101 DAC121S101-Q1 20114923.png Figure 10. INL vs. VA
DAC121S101 DAC121S101-Q1 20114951.png Figure 12. 5-V DNL vs. fSCLK
DAC121S101 DAC121S101-Q1 20114925.png Figure 14. 5-V DNL vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114928.png Figure 16. 3-V INL vs. fSCLK
DAC121S101 DAC121S101-Q1 20114930.png Figure 18. 3-V INL vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114932.png Figure 20. 3-V INL vs. Temperature
DAC121S101 DAC121S101-Q1 20114934.png Figure 22. Zero Code Error vs. fSCLK
DAC121S101 DAC121S101-Q1 20114936.png Figure 24. Zero Code Error vs. Temperature
DAC121S101 DAC121S101-Q1 20114938.png Figure 26. Full-Scale Error vs. Clock Duty Cycle
DAC121S101 DAC121S101-Q1 20114944.png Figure 28. Supply Current vs. VA
DAC121S101 DAC121S101-Q1 20114946.png Figure 30. 5-V Glitch Response
DAC121S101 DAC121S101-Q1 20114948.png Figure 32. 3-V Wake-Up Time