SCAS884D August   2009  – December 2015 CDCLVP1102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: LVCMOS Input
    6. 6.6 Electrical Characteristics: Differential Input
    7. 6.7 Electrical Characteristics: LVPECL Output
    8. 6.8 Electrical Characteristics: LVPECL Output
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

Power consumption of the CDCLVP1102 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. That is, as an estimate, ambient temperature (TA) plus device power consumption times RθJA should not exceed 125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. Figure 24 shows a recommended land and via pattern.

11.2 Layout Example

CDCLVP1102 ai_land_pattern_cas884.gif Figure 24. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVP1102 supports high temperatures on the printed circuit board (PCB) measured at the thermal pad. The system designer needs to ensure that the maximum junction temperature is not exceeded. Ψjb can allow the system designer to measure the board temperature with a fine gauge thermocouple and back calculate the junction temperature using Equation 1. Note that Ψjb is close to RθJB as 75 to 95% of a device's heat is dissipated by the PCB. Further information can be found at SPRA953 and SLUA566.

Equation 1. Tjunction = TPCB + ( Ψjb × Power)
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TPCB = 105 °C
Ψjb = 21.7 °C/W
PowerinclTerm = Imax × Vmax = 105 mA × 3.6 V = 378 mW (max power consumption including termination resistors)
PowerexclTerm = 302.5 mW (max power consumption excluding termination resistors, see SLYT127 for further details)
ΔTJunction = Ψjb × PowerexclTerm = 21.7 °C/W × 302.5 mW = 6.56 °C
TJunction = ΔTJunction + TChassis = 6.56 °C + 105 °C = 111.56 °C (the maximum junction temperature of 125 °C is not violated)