SLAS564G August   2007  – October 2016 CDCE937 , CDCEL937

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: CLK_IN
    7. 6.7 Timing Requirements: SDA/SCL
    8. 6.8 EEPROM Specification
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
      3. 8.3.3 SDA/SCL Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA/SCL Hardware Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 SDA/SCL Configuration Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCEx937 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer. It can be used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCEx937 features an on-chip loop filter and spread-spectrum modulation. Programming can be done through SPI, pin-mode, or using on-chip EEPROM. The following section shows some examples of using CDCEx937 in various applications.

9.2 Typical Application

Figure 14 shows the use of the CDCEx937 devices for replacement of crystals and crystal oscillators on a Gigabit Ethernet Switch application.

CDCE937 CDCEL937 CDCE9_Typ_App.gif Figure 14. Crystal and Oscillator Replacement Example

9.2.1 Design Requirements

CDCEx937 supports spread-spectrum clocking (SSC) with multiple control parameters:

  • Modulation amount (%)
  • Modulation frequency (>20 kHz)
  • Modulation shape (triangular)
  • Center spread / down spread (± or –)

CDCE937 CDCEL937 mod_freq_mod_amount.png Figure 15. Modulation Frequency (fm) and Modulation Amount

9.2.2 Detailed Design Procedure

9.2.2.1 Spread Spectrum Clock (SSC)

Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread spectrum can reduce Electromagnetic Interference (EMI) by reducing the level of emission from clock distribution network.

CDCE937 CDCEL937 comparison_typ_clock_pwr_spec_spred_spec.gif
CDCS502 with a 25-MHz Crystal, FS = 1, Fout = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 16. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock

9.2.2.2 PLL Frequency Planning

At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCEx913 are calculated with Equation 1.

Equation 1. CDCE937 CDCEL937 q1_fout_cas847.gif

where

  • M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
  • Pdiv (1 to 127) is the output divider

The target VCO frequency (ƒVCO) of each PLL is calculated with Equation 2.

Equation 2. CDCE937 CDCEL937 q2_fvco_cas847.gif

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

  • N
  • P = 4 – int(log2N/M; if P < 0 then P = 0
  • Q = int(N'/M)
  • R = N′ – M × Q

where

N′ = N × 2P

N ≥ M;

80 MHz ≤ ƒVCO ≤ 230 MHz

16 ≤ Q ≤ 63

0 ≤ P ≤ 4

0 ≤ R ≤ 51

Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2 for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz → fOUT = 74.25 MHz
→ fVCO = 108 MHz → fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2 → P = 4 – int(log25.5) = 4 – 2 = 2
→ N' = 4 × 22 = 16 → N' = 11 × 22 = 44
→ Q = int(16) = 16 → Q = int(22) = 22
→ R = 16 – 16 = 0 → R = 44 – 44 = 0

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.

9.2.2.3 Crystal Oscillator Start-Up

When the CDCEx937 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time compared to the internal PLL lock time. Figure 17 shows the oscillator start-up sequence for a 27-MHz crystal input with an 8-pF load. The start-up time for the crystal is in the order of approximately 250 µs compared to approximately 10 µs of lock time. In general, lock time will be an order of magnitude less compared to the crystal start-up time.

CDCE937 CDCEL937 crystal_osc_startup_vs_pll_locktime.gif Figure 17. Crystal Oscillator Start-Up vs PLL Lock Time

9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling

The frequency for the CDCEx937 is adjusted for media and other applications with the VCXO control input Vctrl. If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.

CDCE937 CDCEL937 freq_adj_pwm_input.gif Figure 18. Frequency Adjustment Using PWM Input to the VCXO Control

9.2.2.5 Unused Inputs and Outputs

If VCXO pulling functionality is not required, Vctrl should be left floating. All other unused inputs should be set to GND. Unused outputs should be left floating.

If one output block is not used, TI recommends disabling it. However, TI always recommends providing the supply for the second output block even if it is disabled.

9.2.2.6 Switching Between XO and VCXO Mode

When the CDCEx937 is in crystal oscillator or in VCXO configuration, the internal capacitors require different internal capacitance. The following steps are recommended to switch to VCXO mode when the configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:

  1. While in XO mode, put Vctrl = Vdd / 2
  2. Switch from XO mode to VCXO mode
  3. Program the internal capacitors in order to obtain 0 ppm at the output

9.2.3 Application Curves

Figure 19, Figure 20, Figure 21, and Figure 22 show CDCEx937 measurements with the SSC feature enabled. Device configuration: 27-MHz input, 27-MHz output.

CDCE937 CDCEL937 scas849_appcv1.png Figure 19. fout = 27 MHz, VCO frequency < 125 MHz, SSC (2% center)
CDCE937 CDCEL937 scas849_appcv3.png Figure 21. Output Spectrum With SSC Off
CDCE937 CDCEL937 scas849_appcv2.png Figure 20. fout = 27 MHz, VCO frequency > 175 MHz, SSC (1%, center)
CDCE937 CDCEL937 scas849_appcv4.png Figure 22. Output Spectrum With SSC On, 2% Center