ZHCSPD1D February   1998  – November 2021 CD54HC165 , CD54HCT165 , CD74HC165 , CD74HCT165

PRODUCTION DATA  

  1. 特性
  2. 说明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Reccomended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • J|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

Overview

The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (QH and QH) available from the last stage. When the parallel load (SH/LD) input is LOW, parallel data from the A to H inputs are loaded into the register asynchronously. When the SH/LD is HIGH, data enters the register serially at the SER input and shifts one place to the right (A→B→C, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by connecting the QH output to the SER input of the succeeding device.

For predictable operation the LOW-to-HIGH transition of CLK INH should only take place while CLK is HIGH. Also, CLK and CLK INH should be LOW before the LOW-to-HIGH transition of SH/LD to prevent shifting the data when SH/LD goes HIGH.