ZHCSCS0C September   2014  – March 2017

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Dynamic Rectifier Control
      2. 8.3.2  Dynamic Power Scaling
      3. 8.3.3  VO_REG Calculations
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Adapter Enable Functionality
      6. 8.3.6  Turning Off the Transmitter
        1. 8.3.6.1 WPC v1.2 EPT
      7. 8.3.7  Communication Current Limit
      8. 8.3.8  PD_DET and TMEM
      9. 8.3.9  TS/CTRL
      10. 8.3.10 PMODE Pin
      11. 8.3.11 I2C Communication
      12. 8.3.12 Input Overvoltage
      13. 8.3.13 Alignment Aid Using Frequency Information
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1  Wireless Power Supply Current Register 1
      2. 8.5.2  Wireless Power Supply Current Register 2
      3. 8.5.3  Wireless Power Supply Current Register 3
      4. 8.5.4  I2C Mailbox Register
      5. 8.5.5  I2C Mailbox Register 2
      6. 8.5.6  I2C Mailbox Register 3
      7. 8.5.7  Wireless Power Supply FOD RAM
      8. 8.5.8  Wireless Power User Header RAM
      9. 8.5.9  Wireless Power USER VRECT Status RAM
      10. 8.5.10 Wireless Power VOUT Status RAM
      11. 8.5.11 Wireless Power Proprietary Mode REC PWR MSByte Status RAM
      12. 8.5.12 Wireless Power REC PWR LSByte Status RAM
      13. 8.5.13 Wireless Power Prop Packet Payload RAM Byte 0
      14. 8.5.14 Wireless Power Prop Packet Payload RAM Byte 1
      15. 8.5.15 Wireless Power Prop Packet Payload RAM Byte 2
      16. 8.5.16 Wireless Power Prop Packet Payload RAM Byte 3
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 WPC v1.2 Power Supply 7-V Output With 1.4-A Maximum Current With I2C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Set Point
          2. 9.2.1.2.2 Output and Rectifier Capacitors
          3. 9.2.1.2.3 TMEM
          4. 9.2.1.2.4 Maximum Output Current Set Point
          5. 9.2.1.2.5 I2C
          6. 9.2.1.2.6 Communication Current Limit
          7. 9.2.1.2.7 Receiver Coil
          8. 9.2.1.2.8 Series and Parallel Resonant Capacitors
          9. 9.2.1.2.9 Communication, Boot, and Clamp Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Standalone 10-V WPC v1.2 Power Supply With 1-A Maximum Output Current in System Board
      3. 9.2.3 Standalone 10-V Power Supply With 1-A Maximum Output Current for 2S Charging System
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1  Output Voltage Set Point
          2. 9.2.3.2.2  Output and Rectifier Capacitors
          3. 9.2.3.2.3  TMEM
          4. 9.2.3.2.4  Maximum Output Current Set Point
          5. 9.2.3.2.5  I2C
          6. 9.2.3.2.6  Communication Current Limit
          7. 9.2.3.2.7  Receiver Coil
          8. 9.2.3.2.8  Series Resonant Capacitors
            1. 9.2.3.2.8.1 Tuning Procedure
          9. 9.2.3.2.9  Communication, Boot, and Clamp Capacitors
          10. 9.2.3.2.10 VRECT Clamp
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

WPC-based wireless power systems consist of a charging pad (primary, transmitter) and the secondary-side equipment (receiver). The coils in the charging pad and secondary equipment magnetically couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the secondary by transformer action between the coils. The receiver can achieve control over the amount of power transferred by getting the transmitter to change the field strength by changing the frequency, duty cycle, or voltage rail energizing the primary coil.

The receiver equipment communicates with the primary by modulating the load seen by the primary. This load modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and demodulated by the transmitter.

In WPC, the system communication is digital (packets that are transferred from the secondary to the primary). Differential biphase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication packets are defined. These include identification and authentication packets, error packets, control packets, power usage packets, and end power transfer packets, among others.

The bq51025 incorporates a two-way proprietary authentication with the bq500215 primary controller that allows optimal power transfer and system performance up to 10-W output power while still complying with WPC v1.2 specifications.

bq51025 desc_overview_bq51025.jpg Figure 6. Wireless Power System Indicating the Functional Integration of the bq51025

The bq51025 device integrates fully-compliant WPC v1.2 communication protocol to streamline the wireless power receiver designs (no extra software development required). Other unique algorithms such as Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the smallest solution size of the industry.

As a WPC system, when the receiver (shown in Figure 6) is placed on the charging pad, the secondary coil couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the LDO which feeds the output.

The bq51025 device identifies and authenticates itself to the primary using the COMMx pins, switching on and off the COMM FETs, and hence, switching in and out COMM capacitors. If the authentication is successful, the primary remains powered-up. Using a proprietary authentication protocol, the bq51025 determines if the 10-W bq500215 primary controller is powering the device, in which case the bq51025 device allows operation up to 10-W. If the bq51025 determines that a standard WPC-compliant transmitter is powering it, it allows operation up to 5-W. The bq51025 device measures the voltage at the RECT pin, calculates the difference between the actual voltage and the desired voltage VRECT(REG) and sends back error packets to the transmitter. This process goes on until the input voltage settles at VRECT(REG) MAX. During a load change, the dynamic rectifier algorithm sets the target voltage between VRECT(REG) MAX and VRECT(REG) MIN, as shown in Table 1. This algorithm enhances the transient response of the power supply.

After the voltage at the RECT pin is at the desired value, the pass FET is enabled. The voltage control loop ensures that the output voltage is maintained at VOUT(REG), powering the downstream charger. The bq51025 device meanwhile continues to monitor the input voltage, and keeps sending control error packets (CEP) to the primary, on average, every 250 ms. If a large transient occurs, the feedback to the primary speeds up to 32-ms communication periods to converge on an operating point in less time.

Functional Block Diagram

bq51025 FBD_SLUSBX7.gif

Feature Description

Dynamic Rectifier Control

The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given maximum output current setting. This is achieved by providing enough voltage headroom across the internal regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target. Therefore, a transient response depends on the loosely-coupled transformer's output-impedance profile. The Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed at the output of the internal regulator (output of the bq51025 device). A 1-A application allows up to a 2-Ω output impedance. Figure 13 shows the Dynamic Rectifier Control behavior during active power transfer.

Dynamic Power Scaling

The Dynamic Power Scaling feature allows for the loss characteristics of the bq51025 device to be scaled based on the maximum expected output power in the end application. This effectively optimizes the efficiency for each application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the maximum output current. Note that the maximum output current is set by the KILIM term and the RILIM resistance (where RILIM = KILIM / IILIM). The flow diagram in Figure 13 shows how the rectifier is dynamically controlled (Dynamic Rectifier Control) based on the voltage level at the ILIM pin (VILIM). This voltage represents a fixed percentage of the IILIM setting. Table 1 summarizes how the rectifier behavior is dynamically adjusted based on two different RILIM settings. Table 1 is shown for IMAX, which is the maximum operating output current and is typically lower than IILIM (about 20% lower). See RILIM Calculations for more details on how to set IILIM.

Table 1. Dynamic Rectifier Regulation(1)

Output Current Percentage
(Low-Power Mode)
Output Current Percentage
(Proprietary Mode)
Low Power (5-W) Mode
RILIM = 700 Ω
IILIM = 0.6 A
(IMAX = 0.5 A)
Low Power (5-W) Mode
RILIM = 700 Ω
IILIM = 1.2 A
(IMAX = 1 A)
Proprietary 10-W Mode
RILIM = 495 Ω
IILIM = 1.7 A
(IMAX = 1.4 A)
VRECT (2)
0 to 10% 0 to 5% 0 to 0.05 A 0 to 0.05 A 0 to 0.070 A VOUT + 2.0
10 to 20% 5 to 10% 0.05 to 0.1 A 0.05 to 0.1 A 0.070 to 0.14 A VOUT + 1.6
20 to 40% 10 to 20% 0.1 to 0.2 A 0.1 to 0.2 A 0.14 to 0.28 A VOUT + 0.6
>40% >20% >0.2 A >0.2 A >0.28 A VOUT + 0.12
ROS = Open. The relation between VILIM and ILIM has some dependency on the ROS value.
VRECT is regulated to a maximum of 11 V.

Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different RILIM settings. With the rectifier voltage (VRECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where,

Equation 1. bq51025 eq_dynamic_pwr_scal_SLUSBS9.gif

Figure 22 shows how the Dynamic Power Scaling feature reduces the VRECT with increased load, allowing the post-regulation LDO to have maximum headroom at low load conditions for better load transient performance and minimal power dissipation at high loads. Note that this feature balances efficiency with optimal system transient response.

VO_REG Calculations

The bq51025 device allows the designer to set the output voltage by setting a feedback resistor divider network from the OUT pin to the VO_REG pin, as seen in Figure 7. Select the resistor divider network so that the voltage at the VO_REG pin is 0.5 V (default setting) at the desired output voltage. The target VO_REG voltage can be changed through I2C by changing Table 4

bq51025 VO_REG_net_LUSBS9.gif Figure 7. VO_REG Network

Choose the desired output voltage VOUT and R6:

Equation 2. bq51025 eq_Kvo_SLUSBS9.gif
Equation 3. bq51025 eq_R6_voltage_SLUSBS9.gif

RILIM Calculations

The bq51025 device includes a means of providing hardware overcurrent protection (IILIM) through an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, current compliance). The RILIM resistor size also sets the thresholds for the dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The calculation for the total RILIM resistance is as follows:

Equation 4. bq51025 eq_R_ilim_1_LUSBX7.gif
Equation 5. bq51025 eq_R1_1_LUSBX7.gif

The RILIM allows for the ILIM pin to reach 1.2 V when operating in proprietary mode (up to 10-W output power) when the output current is equal to IILIM. When the receiver operates in standard WPC low-power mode, the ILIM pin voltage threshold is changed from 1.2 to 0.6 V, setting the low-power mode current limit to half of that at the proprietary mode setting.

In the case where having the current limit change by a factor of two between modes is not desired, the two current limit levels may be independently controlled in two ways:

  • By programming the IO_REG level through I2C
  • By changing the effective RILIM value for each mode by using an external switch controlled by the PMODE pin

To adjust the current limit for each mode through I2C, RILIM is chosen using Equation 4 where IILIM is the current limit for proprietary mode (that is, higher current setting). The host should first set the desired current limit value for low-power mode as a percentage of IILIM through the IO_REG bits and then disable the 2X current scaling by setting the I2C_ILIM bit in Table 5 and Table 6 respectively to enable programmability. By default, IO_REG is set to the highest current setting allowed by RILIM (that is, 100% of IILIM).

If I2C control is not available, the current limit for low power and proprietary modes can be set independently by shorting a portion of the R1 resistance using an external switch as shown in Figure 8. RILIM is calculated using Equation 4, where IILIM is the desired current limit for proprietary mode. The resistance to set the current limit in low-power mode, RILIM_LP is calculated by Equation 6.

Equation 6. bq51025 eq_Rilim_5W.gif

where

The value for R1_A is given by RILIM_LP – RFOD. The value of R1_B is then RILIM – R1_A – RFOD. Note that with this method IILIM must be less than 2 × IILIM_LP

bq51025 Ilim_swicth.gif Figure 8. Current Limit Setting for bq51025 Using External Switch

When choosing IILIM, consider the following two possible operating conditions:

  • If the user's application requires an output current equal to or greater than the external IILIM that the circuit is designed for (input current limit on the charger where the receiver device is tied higher than the external IILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output does not drop to zero. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the charger pulls the output of the receiver device to ground when the receiver device enters current regulation.
  • If the user's applications are designed to extract less than the IILIM, typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input current limit on the charger lower than the external ILIM of the receiver device.

However, in both cases, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC communication. The following calculations show how such a design is achieved:

Equation 7. bq51025 eq_R_ilim_2_LUSBX7.gif
Equation 8. bq51025 eq_R1_1_LUSBX7.gif

where

When referring to the application diagram shown in Typical Applications, RILIM is the sum of the R1 and RFOD resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the application. To obtain the tool for calculating RFOD, contact your TI representative. Use RFOD to allow the receiver implementation to comply with WPC v1.2 requirements related to received power accuracy.

Adapter Enable Functionality

The bq51025 device can also help manage the multiplexing of adapter power to the output and can shut off the TX when the adapter is plugged in and is above the VAD-EN. After the adapter is plugged in and the output turns off, the RX device sends an EPT to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V below AD, which allows the device to turn on the back-to-back PMOS connected between AD and OUT (see Figure 32).

Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. Note that it is required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions. Also, when AD mode is enabled, no load can be pulled from the RECT pin because this could cause an internal device overvoltage in the bq51025 device.

Turning Off the Transmitter

The WPC v1.2 specification allows the receiver to turn off the transmitter and put the system in a low-power standby mode. There are two different ways to accomplish this with the bq51025 device. The EPT charge complete (WPC) can be sent to the TX by pulling the TS pin high (above 1.4 V). The bq51025 device will then sense this and send the appropriate signal to the TX, thus putting the TX in a low-power standby mode.

WPC v1.2 EPT

The WPC allows for a special command to terminate power transfer from the TX-termed EPT packet. The WPC v1.2 specifies the following reasons and their corresponding data field value in Table 2.

Table 2. EPT Codes in WPC

Reason Value Condition(1)
Unknown 0x00 AD > 3.6 V
Charge complete 0x01 TS/CTRL > 1.4 V
Internal fault 0x02 TJ > 150°C or RILIM < 215 Ω
Over temperature 0x03 TS < VHOT, or TS/CTRL < 100 mV (2)
Over voltage 0x04 VRECT voltage does not converge and stays higher than target
Battery failure 0x06 Not sent
Reconfigure 0x07 Not sent
No response 0x08 Not sent
The Condition column corresponds to the case where the bq51025 device sends the WPC EPT command.
The TS < VTS-HOT condition refers to using an external thermistor for temperature control. The TS/CTRL <100-mV condition refers to driving the TS/CTRL pin from external GPIO.

Communication Current Limit

Communication current limit is a feature that allows for error-free communication to happen between the RX and TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current during communication with the TX. The communication current limit is set according to Table 3. The communication current limit can be enabled by pulling CM_ILIM pin low or disabled by pulling the CM_ILIM pin high (>1.4 V) . An internal pulldown enables communication current limit when the CM_ILIM pin is left floating.

Table 3. Communication Current Limit

IOUT Communication Current Limit
0 mA < IOUT < 100 mA None
100 mA < IOUT < 400 mA IOUT + 50 mA
400 mA < IOUT < Max current IOUT – 50 mA

When the communication current limit is enabled, the amount of current that the load can draw is limited. If the charger in the system does not have a VIN-DPM feature, the output of the receiver collapses if communication current limit is enabled. Please note that power dissipation within the device will increase during current limiting, lowering overall system efficiency. To disable communication current limit, pull CM_ILIM pin high.

PD_DET and TMEM

PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET is low. The voltage on the TMEM pin depends on capturing the energy from the digital ping from the transmitter and storing it on the C5 capacitor in Figure 9. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a low-power mode. However, it continues to check if the receiver would like to renegotiate a power transfer by periodically performing the digital ping. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes the capacitor. The designer can choose a bleedoff resistor, RMEM, in parallel with C5 that sets the time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is indeterminate and depends on each transmitter manufacturer.

bq51025 desc_TMEM_config_SLUSBS9.gif Figure 9. TMEM Configuration

Set capacitor on C5 = TMEM to 2.2 µF. Resistor RMEM across C5 can be set by understanding the duration between digital pings (tping). Set the resistor such that:

Equation 9. bq51025 eq_Rmem.gif

PD_DET typically requires a pullup resistor to an external source. A higher current through the PD_DET pin may affect the output regulation of the device. To improve regulation, TI recommends pullup resistor values in the range of 15 to 100 kΩ.

TS/CTRL

The bq51025 device includes a ratiometric external temperature sense function. The temperature sense function has a low ratiometric threshold which represents a hot condition. TI recommends an external temperature sensor to provide safe operating conditions for the receiver product. This pin is best used for monitoring the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC) resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel resistor implementation for setting the threshold at which VTS-HOT is reached. When the VTS-HOT threshold is reached, the device will send an EPT – overtemperature signal for a WPC transmitter.

bq51025 det_ntc_setup_SLUSBS9.gif Figure 10. NTC Resistor Setup

Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of VTS-HOT. After the NTC is chosen and RNTCHOT at VTS-HOT is determined from the data sheet of the NTC, use Equation 10 to calculate R1 and R3. In many cases, depending on the NTC resistor, R1 or R3 can be omitted. To omit R1, set R1 to 0, and to omit R3, set R3 to 10 MΩ in the calculation.

Equation 10. bq51025 eq_Ts-hot_SLUSBS9.gif

PMODE Pin

Connect a 5-MΩ resistor to ground in order to use PMODE to indicate the receiver mode of operation. PMODE is high when in low-power mode and low in proprietary mode. This pin may be used to control the gate of an NMOS switch to change the RILIM, and hence, the current limit based on the maximum power allowed by the transmitter (10 W for bq500215, 5 W or less otherwise). This pin may be left floating if not used. and show the PMODE behavior during startup.

I2C Communication

The bq51025 device allows for I2C communication with the internal CPU. The I2C address for the device is 0x6C. In case the I2C is not used, ground SCL and SDA. See Register Maps for more information.

Input Overvoltage

If the input voltage suddenly increases in potential for some condition (for example, a change in position of the equipment on the charging pad), the voltage-control loop inside the bq51025 device becomes active, and prevents the output from going beyond VOUT(REG). The receiver then starts sending back error packets every 32 ms until the input voltage comes back to an acceptable level, and then maintains the error communication every 250 ms.

If the input voltage increases in potential beyond VRECT_OVP, the device switches off the LDO and informs the primary to terminate power. In addition, a proprietary voltage protection circuit is activated by means of CCLAMP1 and CCLAMP2 that protects the device from voltages beyond the maximum rating of the device.

Alignment Aid Using Frequency Information

The bq51025 device provides the host through I2C with power signal frequency information that would enable it to determine the optimal alignment position on the charging surface of a frequency-controlled transmitter. For these WPC transmitters, the power signal frequency increases as the coupling between the primary and secondary coils increases. By finding the position in the charging pad that has the highest frequency, the host can determine that the best possible alignment with the transmitter coil has been achieved.

The bq51025 continuously stores a measurement of the power signal frequency in I2C register 0xFB to provide the host the information it needs to determine optimal placement. The power signal frequency is given by:

Equation 11. bq51025 eq_frequency.gif

where

Figure 11 shows the expected register values across the frequency range.

bq51025 D014_SLUSBX7.gif Figure 11. I2C Code vs Power Signal Frequency

Device Functional Modes

At startup operation, the bq51025 device must comply with proper handshaking to be granted a power contract from the WPC transmitter. The transmitter initiates the handshake by providing an extended digital ping after analog ping detects an object on the transmitter surface. If a receiver is present on the transmitter surface, the receiver then provides the signal strength, configuration, and identification packets to the transmitter (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent to the transmitter. The only exception is if there is a true shutdown condition on the AD or TS/CTRL pins where the receiver shuts down the transmitter immediately. See Table 2 for details. After the transmitter has successfully received the signal strength, configuration, and identification packets, the receiver is granted a power contract and is then allowed to control the operating point of the power transfer. With the use of the bq51025 device Dynamic Rectifier Control algorithm, the receiver informs the transmitter to adjust the rectifier voltage to approximately 8 V prior to enabling the output supply. For startup flow diagram details, see Figure 12.

To operate in 10-W mode, the bq51025 device performs a proprietary handshaking procedure with the transmitter. If the transmitter (bq500215) responds to the bq51025 handshake, a 10-W power contract is granted and the bq51025 operates in 10-W mode, setting the proper output current limit and control. If there is no response from the transmitter, the bq51025 device defaults to 5-W mode operation.

bq51025 desc_wireless_pwr_SLUSBX7.gif Figure 12. Wireless Power Startup Flow Diagram on WPC TX

After the startup procedure is established, the receiver enters the active-power transfer stage (considered the main loop of operation). The Dynamic Rectifier Control algorithm determines the rectifier voltage target based on a percentage of the maximum output current level setting (set by KILIM and RILIM). The receiver sends control error packets to converge on these targets. As the output current changes, the rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the instantaneous transient response of the system is open loop and dependent on the receiver coil output impedance at that operating point. The main loop also determines if any conditions in Table 2 are true in order to discontinue power transfer. Figure 13 shows the active-power transfer loop.

bq51025 desc_pwr_transfer_SLUSBX7.gif Figure 13. Active Power Transfer Flow Diagram on WPC TX

Register Maps

Locations 0x01 and 0x02 can be written at any time. Locations 0xE0 to 0xFF are only functional when VRECT > VUVLO. When VRECT goes below VUVLO, locations 0xE0 to 0xFF are reset.

Wireless Power Supply Current Register 1

Table 4. Wireless Power Supply Current Register 1 (READ / WRITE)

Memory Location: 0x01, Default State: 00000001
BIT NAME READ / WRITE FUNCTION
B7 (MSB) Read / Write Not used
B6 Read / Write Not used
B5 Read / Write Not used
B4 Read / Write Not used
B3 Read / Write Not used
B2 VOREG2 Read / Write 450, 500, 550, 600, 650, 700, 750, or 800 mV(1)
Changes VO_REG target
Default value 001
B1 VOREG1 Read / Write
B0 VOREG0 Read / Write
Maximum output voltage is limited to 10 V. Maximum VO_REG setting is 0.5 V when default output voltage is set to 10 V with external resistor divider (19:1 ratio)

Wireless Power Supply Current Register 2

Table 5. Wireless Power Supply Current Register 2 (READ / WRITE)

Memory Location: 0x02, Default State: 00000111
BIT NAME READ / WRITE FUNCTION
B7 (MSB) JEITA Read / Write Not used
B6 Read / Write Not used
B5 ITERM2 Read / Write Not used.
B4 ITERM1 Read / Write
B3 ITERM0 Read / Write
B2 IOREG2 Read / Write 10%, 20%, 30%, 40%, 50%, 60%, 80%, and 100% of IILIM current based on configuration
000, 001, ….111
B1 IOREG1 Read / Write
B0 IOREG0 Read / Write

Wireless Power Supply Current Register 3

Table 6. Wireless Power Supply Current Register 3 (READ / WRITE)

Memory Location: 0xF0, Reset State: 00000000
BIT NAME READ / WRITE FUNCTION
B7 Reserved Read/Write
B6 Reserved Read / Write
B5 Reserved Read / Write
B4 Reserved Read / Write
B3 Reserved Read / Write
B2 Reserved Read / Write
B1 I2C_ILIM Read / Write Set bit to 1 to disable 2× current limit scaling between low-power and proprietary modes. Must be set to 1 to correctly adjust the current limit for each mode through I2C
B0 Reserved Read / Write

I2C Mailbox Register

Table 7. I2C Mailbox Register (READ / WRITE)

Memory Location: 0xE0, Reset State: 10000000
BIT NAME READ / WRITE FUNCTION
B7 USER_PKT_DONE Read/Write Set bit to 0 to send proprietary packet with header in 0xE2.
CPU checks header to pick relevant payload from 0xF1 to 0xF4
This bit will be set to 1 after the user packet with the header in register 0xE2 is sent.
B6 USER_PKT_ERR Read 00 = No error in sending packet
01 = Error: No transmitter present
10 = Illegal header found: packet will not be sent
11 = Error: Not defined yet
B5
B4 FOD Mailer Read / Write Not used
B3 ALIGN Mailer Read / Write Setting this bit to 1 enables alignment aid mode where the CEP = 0 is sent until this bit is set to 0 (or CPU reset occurs)
B2 FOD Scaler Read / Write Not used, write to 0 if register is written
B1 Reserved Read / Write
B0 Reserved Read / Write

I2C Mailbox Register 2

Table 8. I2C Mailbox Register 2 (READ / WRITE)

Memory Location: 0xEF, Reset State: 00000000
BIT NAME READ / WRITE FUNCTION
B7 PMODE Read Power mode
0 = Low-power mode 5 W
1 = Proprietary 10 W
B6 Reserved Read / Write
B5 Reserved Read / Write
B4 Reserved Read / Write
B3 Reserved Read / Write
B2 Reserved Read / Write
B1 Reserved Read / Write
B0 Reserved Read / Write

I2C Mailbox Register 3

Table 9. I2C Mailbox Register 3 (READ)

Memory Location: 0xFB, Reset State: 00000000
BIT NAME READ / WRITE FUNCTION
B7 FREQ7 Read Power signal frequency. See Equation 11 for calculation.
B6 FREQ6 Read
B5 FREQ5 Read
B4 FREQ4 Read
B3 FREQ3 Read
B2 FREQ2 Read
B1 FREQ1 Read
B0 FREQ0 Read

Wireless Power Supply FOD RAM

Table 10. Wireless Power Supply FOD RAM (READ / WRITE)

Memory Location: 0xE1, Reset State: 00000000(1)
BIT NAME READ / WRITE FUNCTION
B7 (MSB) ESR_ENABLE Read / Write Enables I2C based ESR in received power, Enable = 1, Disable = 0
B6 OFF_ENABLE Read / Write Enables I2C based offset power, Enable = 1, Disable = 0
B5 RoFOD5 Read / Write 000 = 0 mW
001 = 78 mW
010 = 156 mW
011 = 234 mW
100 = 312 mW
101 = 390 mW
110 = 468 mW
111 = 546 mW
The value is added to received power message
B4 RoFOD4 Read / Write
B3 RoFOD3 Read / Write
B2 RsFOD2 Read / Write 000 = ESR
001 = ESR
010 = ESR × 2
011 = ESR × 3
100 = ESR × 4
101 = ESR
110 = ESR
111 = ESR x 0.5
B1 RsFOD1 Read / Write
B0 RsFOD0 Read / Write
A non-zero value changes the I2R calculation resistor and offset in the received power calculation by a factor shown in the table.

Wireless Power User Header RAM

Table 11. Wireless Power User Header RAM (WRITE)

Memory Location: 0xE2, Reset State: 00000000(1)
BIT READ / WRITE
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write
Must write a valid WPC v1.2 Proprietary Packet Header to enable proprietary package. Reserved headers (Control Error Packet, Received Power Packet, and so forth) may not be used. As soon as mailer (0xE0) is written, payload bytes are sent on the next available communication slot as determined by CPU. When payload is sent, the mailer (USER_PKT_DONE) is set to 1.

Wireless Power USER VRECT Status RAM

Table 12. Wireless Power USER VRECT Status RAM (READ)

Memory Location: 0xE3, Reset State: 00000000
Range – 0 to 12 V
This register reads back the VRECT voltage with LSB = 46 mV
BIT NAME READ / WRITE FUNCTION
B7 (MSB) VRECT7 Read LSB = 46 mV
B6 VRECT6 Read
B5 VRECT5 Read
B4 VRECT4 Read
B3 VRECT3 Read
B2 VRECT2 Read
B1 VRECT1 Read
B0 VRECT0 Read

Wireless Power VOUT Status RAM

Table 13. Wireless Power VOUT Status RAM (READ)

Memory Location: 0xE4, Reset State: 00000000
This register reads back the VOUT voltage with LSB = 46 mV
BIT NAME Read / Write FUNCTION
B7 (MSB) VOUT7 Read / Write LSB = 46 mV
B6 VOUT6 Read / Write
B5 VOUT5 Read / Write
B4 VOUT4 Read / Write
B3 VOUT3 Read / Write
B2 VOUT2 Read / Write
B1 VOUT1 Read / Write
B0 VOUT0 Read / Write

Wireless Power Proprietary Mode REC PWR MSByte Status RAM

Table 14. Wireless Power Proprietary Mode REC PWR MSByte Status RAM (READ)(1)

Memory Location: 0xE7, Reset State: 00000000
This register reads back the MSByte for received power in Proprietary 10-W Mode only
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write
For proprietary mode, Received power (mW) = (10000/128) × REC PWR MSByte + (10000 / (256 × 128)) × REC PWR LSByte

Wireless Power REC PWR LSByte Status RAM

Table 15. Wireless Power REC PWR LSByte Status RAM (READ)(1)

Memory Location: 0xE8, Reset State: 00000000
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write
This register reads back the received power in low-power mode with LSB = 39 mW. In proprietary mode, this register reads back the LSByte for received power.

Wireless Power Prop Packet Payload RAM Byte 0

Table 16. Wireless Power Prop Packet Payload RAM Byte 0 (WRITE)

Memory Location: 0xF1, Reset State: 00000000
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write

Wireless Power Prop Packet Payload RAM Byte 1

Table 17. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE)

Memory Location: 0xF2, Reset State: 00000000
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write

Wireless Power Prop Packet Payload RAM Byte 2

Table 18. Wireless Power Prop Packet Payload RAM Byte 2 (WRITE)

Memory Location: 0xF3, Reset State: 00000000
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write

Wireless Power Prop Packet Payload RAM Byte 3

Table 19. Wireless Power Prop Packet Payload RAM Byte 3 (WRITE)

Memory Location: 0xF4, Reset State: 00000000
BIT Read / Write
B7 (MSB) Read / Write
B6 Read / Write
B5 Read / Write
B4 Read / Write
B3 Read / Write
B2 Read / Write
B1 Read / Write
B0 Read / Write