ZHCSAI5C November   2012  – November 2021

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Digital Input and Output DC Characteristics
    7. 7.7  Power-on Reset
    8. 7.8  2.5-V LDO Regulator
    9. 7.9  Internal Clock Oscillators
    10. 7.10 ADC (Temperature and Cell Measurement) Characteristics
    11. 7.11 Integrating ADC (Coulomb Counter) Characteristics
    12. 7.12 Data Flash Memory Characteristics
    13. 7.13 I2C-Compatible Interface Communication Timing Requirements
    14. 7.14 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 BAT INSERT CHECK Mode
        2. 8.4.1.2 NORMAL Mode
        3. 8.4.1.3 SLEEP Mode
      2. 8.4.2 SLEEP+ Mode
      3. 8.4.3 HIBERNATE Mode
    5. 8.5 Programming
      1. 8.5.1 Standard Data Commands
      2. 8.5.2 Extended Data Commands
      3. 8.5.3 Communications
        1. 8.5.3.1 I2C Interface
        2. 8.5.3.2 I2C Time Out
        3. 8.5.3.3 I2C Command Waiting Time
        4. 8.5.3.4 I2C Clock Stretching
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 BAT Voltage Sense Input
        2. 9.2.2.2 SRP and SRN Current Sense Inputs
        3. 9.2.2.3 Sense Resistor Selection
        4. 9.2.2.4 TS Temperature Sense Input
        5. 9.2.2.5 Thermistor Selection
        6. 9.2.2.6 REGIN Power Supply Input Filtering
        7. 9.2.2.7 VCC LDO Output Filtering
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Sense Resistor Connections
      2. 11.1.2 Thermistor Connections
      3. 11.1.3 High-Current and Low-Current Path Separation
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.13 I2C-Compatible Interface Communication Timing Requirements

TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
MINNOMMAXUNIT
trSCL or SDA rise time300ns
tfSCL or SDA fall time300ns
tw(H)SCL pulse duration (high)600ns
tw(L)SCL pulse duration (low)1.3μs
tsu(STA)Setup for repeated start600ns
td(STA)Start to first falling edge of SCL600ns
tsu(DAT)Data setup time100ns
th(DAT)Data hold time0ns
tsu(STOP)Setup time for stop600ns
t(BUF)Bus free time between stop and start66μs
fSCLClock frequency (1)400kHz
(1) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See Section 8.5.3.1 and Section 8.5.3.3).
GUID-0A5CBC79-43E7-426C-95F9-B5B7B0FEE9D2-low.gifFigure 7-1 I2C-Compatible Interface Timing Diagrams