ZHCSG50B March   2016  – March 2017

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. 说明 (续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Device Power-On-Reset (POR)
      2. 9.2.2  Device Power Up from Battery without Input Source
      3. 9.2.3  Device Power Up from Input Source
        1. 9.2.3.1 Power Up REGN Regulation (LDO)
        2. 9.2.3.2 Poor Source Qualification
        3. 9.2.3.3 Input Source Type Detection
          1. 9.2.3.3.1 D+/D- Detection Sets Input Current Limit (bq25898D)
          2. 9.2.3.3.2 PSEL Pin Sets Input Current Limit (bq25898)
          3. 9.2.3.3.3 Force Input Current Limit Detection
        4. 9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5 Converter Power-Up
      4. 9.2.4  Input Current Optimizer (ICO)
      5. 9.2.5  Boost Mode Operation from Battery
      6. 9.2.6  Power Path Management
        1. 9.2.6.1 Narrow VDC Architecture
        2. 9.2.6.2 Dynamic Power Management
        3. 9.2.6.3 Supplement Mode
      7. 9.2.7  Battery Charging Management
        1. 9.2.7.1 Autonomous Charging Cycle
        2. 9.2.7.2 Battery Charging Profile
        3. 9.2.7.3 Charging Termination
        4. 9.2.7.4 Resistance Compensation (IRCOMP)
        5. 9.2.7.5 Thermistor Qualification
          1. 9.2.7.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6 Charging Safety Timer
      8. 9.2.8  Battery Monitor
      9. 9.2.9  Status Outputs (PG, STAT, and INT)
        1. 9.2.9.1 Power Good Indicator (PG)
        2. 9.2.9.2 Charging Status Indicator (STAT)
        3. 9.2.9.3 Interrupt to Host (INT)
      10. 9.2.10 BATFET (Q4) Control
        1. 9.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3 BATFET Full System Reset
      11. 9.2.11 Current Pulse Control Protocol
      12. 9.2.12 Input Current Limit on ILIM
      13. 9.2.13 Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1 Thermal Protection in Buck Mode
          1. 9.2.13.1.1 Thermal Protection in Boost Mode
      14. 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1 Input Overvoltage (ACOV)
          2. 9.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2 Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1 VBUS Overcurrent Protection
          2. 9.2.14.2.2 Boost Mode Overvoltage Protection
      15. 9.2.15 Battery Protection
        1. 9.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2 Battery Over-Discharge Protection
        3. 9.2.15.3 System Overcurrent Protection
      16. 9.2.16 Serial Interface
        1. 9.2.16.1 Data Validity
        2. 9.2.16.2 START and STOP Conditions
        3. 9.2.16.3 Byte Format
        4. 9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5 Slave Address and Data Direction Bit
        6. 9.2.16.6 Single Read and Write
        7. 9.2.16.7 Multi-Read and Multi-Write
    3. 9.3 Device Functional Modes
      1. 9.3.1 Host Mode and Default Mode
    4. 9.4 Register Map
      1. 9.4.1  REG00
      2. 9.4.2  REG01
      3. 9.4.3  REG02
      4. 9.4.4  REG03
      5. 9.4.5  REG04
      6. 9.4.6  REG05
      7. 9.4.7  REG06
      8. 9.4.8  REG07
      9. 9.4.9  REG08
      10. 9.4.10 REG09
      11. 9.4.11 REG0A
      12. 9.4.12 REG0B
      13. 9.4.13 REG0C
      14. 9.4.14 REG0D
      15. 9.4.15 REG0E
      16. 9.4.16 REG0F
      17. 9.4.17 REG10
      18. 9.4.18 REG11
      19. 9.4.19 REG12
      20. 9.4.20 REG13
      21. 9.4.21 REG14
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application Diagram
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Buck Input Capacitor
        3. 10.2.2.3 System Output Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

The device is a highly integrated 4-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2) , low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap diode for the high-side gate drive.

Functional Block Diagram

bq25898 bq25898D fbd3_slusca6.gif

Feature Description

Device Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET (see Supplement Mode). When the system is overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and sets BATFET_DIS bit to indicate BATFET is disabled until the input source plugs in again or one of the methods describe in BATFET Enable (Exit Shipping Mode) is applied to re-enable BATFET.

Device Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started when AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:

  1. Power Up REGN LDO
  2. Poor Source Qualification
  3. Input Source Type Detection based on D+/D- (bq25898D) or PSEL (bq25898) to set default Input Current Limit (IINLIM) register and input source type
  4. Input Voltage Limit Threshold Setting (VINDPM threshold)
  5. Converter Power-up

Power Up REGN Regulation (LDO)

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The REGN is enabled when all the below conditions are valid.

  1. VBUS above VVBUS_UVLOZ
  2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
  3. After 220 ms delay is completed

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements in order to start the buck converter.

  1. VBUS voltage below VACOV
  2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection when AUTO_DPDM_EN bit is set.

The bq25898D follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source (SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it initiates adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake when MAXC_EN or HVDCP_EN is set. The bq25898 sets input current limit through PSEL and OTG pins.

After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin are changed:

  1. Input Current Limit (IINLIM) register is changed to set current limit
  2. PG_STAT bit is set
  3. PG pin goes low (bq25898)

The host can over-write IINLIM register to change the input current limit if needed. The charger input current is always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO) is enable or disabled.

When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit (IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.

D+/D– Detection Sets Input Current Limit (bq25898D)

The bq25898D contains a D+/D– based input source detection to set the input current limit automatically. The D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard adapter detection is applied to set the input current limit.

When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge™, etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be disabled by clearing MAXC_EN and/or HVDCP_EN bits .

bq25898 bq25898D DD_detection2_slusbu7.gif Figure 11. USB D+/D- Detection

Table 1. Non-Standard Adapter Detection

NON-STANDARD ADAPTER D+ THRESHOLD D- THRESHOLD INPUT CURRENT LIMIT
Divider 1 VD+ within V2P7_VTH VD- within V2P0_VTH 2.1A
Divider 2 VD+ within V1P2_VTH VD- within V1P2_VTH 2A
Divider 3 VD+ within V2P0_VTH VD- within V2P7_VTH 1A
Divider 4 VD+ within V2P7_VTH VD- within V2P7_VTH 2.4A

Table 2. Adjustable High Voltage Adapter D+/D- Output Configurations

ADJUSTABLE HIGH VOLTAGE HANDSHAKE D+ D- OUTPUT
MaxCharge (12V) I1P6MA_ISINK V3p45_VSRC 12 V
MaxCharge (9V) V3p45_VSRC I1P6MA_ISINK 9 V

After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following registers including Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:

Table 3. bq25898D Result

D+/D- DETECTION INPUT CURRENT LIMIT (IINLIM) SDP_STAT VBUS_STAT
USB SDP (USB500) 500 mA 1 001
USB CDP 1.5 A 1 010
USB DCP 3.25 A 1 011
Divider 3 1 A 1 110
Divider 1 2.1 A 1 110
Divider 4 2.4 A 1 110
Divider 2 2 A 1 110
MaxCharge 1.5 A 1 100
Unknown Adapter 500 mA 1 101

PSEL Pin Sets Input Current Limit (bq25898)

The bq25898 has PSEL interface for input current limit setting to interface with USB PHY. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. To implement USB100 in the system, the host can enter HiZ mode by setting EN_HIZ bit after 2 min charging with 500 mA input current limit.

Table 4. bq25898 Result

INPUT DETECTION BAT VOLTAGE PSEL PIN INPUT CURRENT LIMIT (IINLIM) SDP_STAT VBUS_STAT
USB SDP (USB500) X High 500 mA 1 001
Adapter X Low 3.25 A 1 010

Force Input Current Limit Detection

In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed, FORCE_DPDM bit returns to 0 by itself and Input Result is updated.

Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.

  1. Absolute VINDPM (FORCE_VINDPM=1)
  2. By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM is writable and allows host to set the absolute threshold of VINDPM function.

  3. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)

When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.

After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.

Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the device limits input current to the lower value of ILIM pin and IILIM register (ICO_EN = 0) or IDPM_LIM register (ICO_EN = 1).

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

Input Current Optimizer (ICO)

The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without overload the input source. The algorithm automatically identify maximum input current limit of power source without entering VINDPM to avoid input source overload.

This feature is enabled by default (ICO_EN=1) and can be disabled by setting ICO_EN bit to 0. After DCP or MaxCharge type input source is detected based on the procedures previously described (Input Source Type Detection). The algorithm runs automatically when ICO_EN bit is set. The algorithm can also be forced to execute by setting FORCE_ICO bit regardless of input source type detected.

The actual input current limit used by the Dynamic Power Management is reported in IDPM_LIM register while Input Current Optimizer is enabled (ICO_EN = 1) or set by IINLIM register when the algorithm is disabled (ICO_EN = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin function.

Boost Mode Operation from Battery

The device supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA (BOOST_LIM bits = 000) output requirement. The maximum output current is up to 2.4 A. The boost operation can be enabled if the conditions are valid:

  1. BAT above BATLOWV
  2. VBUS less than BAT+VSLEEP (in sleep mode)
  3. Boost mode operation is enabled (OTG pin HIGH and OTG_CONFIG bit =1)
  4. Voltage at TS (thermistor) pin is within range configured by Boost Mode Temperature Monitor as configured by BHOT and BCOLD bits
  5. After 30 ms delay from boost mode enable

In boost mode, the device employs a 500 KHz or 1.5 MHz (selectable using BOOST_FREQ bit) step-up switching regulator based on system requirements. To avoid frequency change during boost mode operations, write to boost frequency configuration bit (BOOST_FREQ) is ignored when OTG_CONFIG is set.

During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5V by default (selectable via BOOSTV register bits) and the output current can reach up to 2.4 A, selected via I2C (BOOST_LIM bits). The boost output is maintained when BAT is above VOTG_BAT threshold.

Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.

bq25898 bq25898D D011_SLUSBU7.gif Figure 12. V(SYS) vs V(BAT)

Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high. Figure 13 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum system voltage setting.

bq25898 bq25898D DPM_responce_slusbu7.gif Figure 13. DPM Response

Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the Supplement Mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDS(ON) until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 14 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit Supplement Mode when the battery is below battery depletion threshold.

bq25898 bq25898D D010_SLUSBU7.gif Figure 14. BATFET V-I Curve

Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 4-A charge current for high capacity battery. The 5-mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

Autonomous Charging Cycle

With battery charging enabled (CHG_CONFIG bit = 1 and CE pin is low), the device autonomously completes a charging cycle without host involvement. The device default charging parameters are listed in Table 5. The host can always control the charging operations and optimize the charging parameters by writing to the corresponding registers through I2C.

Table 5. Charging Parameter Default Setting

DEFAULT MODE bq25898D bq25898
Charging Voltage 4.208 V 4.208 V
Charging Current 2.048 A 2.048 A
Pre-charge Current 128 mA 128 mA
Termination Current 256 mA 256 mA
Temperature Profile JEITA JEITA
Safety Timer 12 hour 12 hour

A new charge cycle starts when the following conditions are valid:

  • Converter starts
  • Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
  • No thermistor fault on TS pin
  • No safety timer fault
  • BATFET is not forced to turn off (BATFET_DIS bit = 0)

The charger device automatically terminates the charging cycle when the charging current is below termination threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.

Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.

Table 6. Charging Current Setting

VBAT CHARGING CURRENT REG DEFAULT SETTING CHRG_STAT
< 2 V IBATSHORT 01
2 V – 3 V IPRECHG 0 mA (precharge disabled) 01
> 3 V ICHG 2048 mA 10

If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

bq25898 bq25898D Battery_Charging_Profile_slusca6.gif Figure 15. Battery Charging Profile

Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn on again to engage Supplement Mode.

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

Resistance Compensation (IRCOMP)

For high current charging system, resistance between charger output and battery cell terminal such as board routing, connector, MOSFETs and sense resistor can force the charging process to move from constant current to constant voltage too early and increase charge time. To speed up the charging cycle, the device provides resistance compensation (IRCOMP) feature which can extend the constant current charge time to delivery maximum power to battery.

The device allows the host to compensate for the resistance by increasing the voltage regulation set point based on actual charge current and the resistance as shown below. For safe operation, the host should set the maximum allowed regulation voltage register (VCLAMP) and the minimum resistance compensation (BATCOMP).

Equation 1. VREG_ACTUAL = VREG + min(ICHRG_ACTUAL x BATCOMP, VCLAMP)

Thermistor Qualification

JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.

The device continuously monitors battery temperature by measuring the voltage between the TS pins and ground, typically determined by a negative temperature coefficient thermistor (NTC) and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the T1–T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range. At cool temperature (T1–T2), JEITA recommends the charge current to be reduced to at least half of the charge current or lower. At warm temperature (T3–T5), JEITA recommends charge voltage below nominal charge voltage.

The device provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm temperature (T3–T5) can be 200 mV below charge voltage (JEITA_VSET=0). The current setting at cool temperature (T1–T2) can be further reduced to 20% or 50% of fast charge current (JEITA_ISET bit).

bq25898 bq25898D TS_resistor_network2_slusca6.gif Figure 16. TS Resistor Network
bq25898 bq25898D JEITA_Guideline_Compliance_slusbu7.gif Figure 17. Charging Values

Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 16, the value RT1 and RT2 can be determined by using Equation 2:

Equation 2. bq25898 bq25898D Eq2_slusca6.gif

Select 0°C to 60°C range for Li-ion or Li-polymer battery,
RTHT1 = 27.28 kΩ
RTHT5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ

During JEITA cool, the bq25898x terminates when the charge current has reached 20% or 50% of termination current setting, depending on the JT_IREDUCE bit. During JEITA warm, the bq25898x terminates when the charge current reaches the termination current setting.

Cold/Hot Temperature Window in Boost Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLD1 to VBHOT2 thresholds unless boost mode temperature is disabled by setting BHOT bits to 11. When temperature is outside of the temperature thresholds, the boost mode is suspended. Once temperature is within thresholds, the boost mode is recovered.

bq25898 bq25898D TS_Boost_lusca6.gif Figure 18. TS Pin Thermistor Sense Thresholds in Boost Mode

Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.

During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

Battery Monitor

The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system voltage, thermistor ratio, and charging current, and charging current based on the device’s modes of operation. The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second continuous conversion.

For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The conversion result is ready after tCONV (maximum 1 second).

For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when CONV_RATE is cleared.

When battery monitor is active, the REGN power is enabled and can increase device quiescent current.

Table 7. Battery Monitor Modes of Operation

PARAMETER REGISTER MODES OF OPERATION
CHARGE MODE BOOST MODE DISABLE CHARGE MODE BATTERY ONLY MODE
Battery Voltage (VBAT) REG0E Yes Yes Yes Yes
System Voltage (VSYS) REG0F Yes Yes Yes Yes
Temperature (TS) Voltage (VTS) REG10 Yes Yes Yes Yes
VBUS Voltage (VVBUS) REG11 Yes Yes Yes NA
Charge Current (IBAT) REG12 Yes NA NA NA

Status Outputs (PG, STAT, and INT)

Power Good Indicator (PG)

In bq25898, the PG goes LOW to indicate a good input source when:

  1. VBUS above VVBUS_UVLO
  2. VBUS above battery (not in sleep)
  3. VBUS below VACOV threshold
  4. VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  5. Completed Input Source Type Detection

Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in Figure 49. The STAT pin function can be disable by setting STAT_DIS bit.

Table 8. STAT Pin State

CHARGING STATE STAT INDICATOR
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (Input overvoltage, TS fault, timer fault, input or system overvoltage)
Boost Mode suspend (due to TS Fault)
blinking at 1 Hz

Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256-µs INT pulse.

  • USB/adapter source identified (through PSEL or DPDM detection, with OTG pin)
  • Good input source detected
    • VBUS above battery (not in sleep)
    • VBUS below VACOV threshold
    • VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  • Input removed
  • Charge Complete
  • Any FAULT event in REG0C

When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively. The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.

BATFET (Q4) Control

BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configurated by BATFET_DLY bit.

BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET to restore system power:

  1. Plug in adapter
  2. Clear BATFET_DIS bit
  3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
  4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping mode

BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged-in. By changing the state of BATFET from off to on, system connects to SYS can be effectively have a power-on-reset. The QON pin supports push-button interface to reset system power without host by change the state of BATFET.

When the QON pin is driven to logic low for tQON_RST (typical 15 seconds) while input source is not plugged in and BATFET is enabled (BATFET_DIS=0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.

Current Pulse Control Protocol

The device provides the control to generate the VBUS current pulse protocol to communicate with adjustable high voltage adapter in order to signal adapter to increase or decrease output voltage. To enable the interface, the EN_PUMPX bit must be set. Then the host can select the increase/decrease voltage pulse by setting one of the PUMPX_UP or PUMPX_DN bit (but not both) to start the VBUS current pulse sequence. During the current pulse sequence, the PUMPX_UP and PUMPX_DN bits are set to indicate pulse sequence is in progress and the device pulses the input current limit between current limit set forth by IINLIM or IDPM_LIM register and the 100mA current limit (IINDPM100_ACC). When the pulse sequence is completed, the input current limit is returned to value set by IINLIM or IDPM_LIM register and the PUMPX_UP or PUMPX_DN bit is cleared. In addition, the EN_PUMPX can be cleared during the current pulse sequence to terminate the sequence and force charger to return to input current limit as set forth by the IINLIM or IDPM_LIM register immediately. When EN_PUMPX bit is low, write to PUMPX_UP and PUMPX_DN bit would be ignored and have no effect on VBUS current limit.

Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as:

Equation 3. bq25898 bq25898D eq_ILIM_slusbu7.gif

The actual input current limit is the lower value between ILIM setting and register setting (IINLIM). For example, if the register setting is 111111 for 3.25 A, and ILIM has a 232-Ω resistor (KILIM = 350 max.) to ground for 1.5 A, the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters input current regulation (Refer to Dynamic Power Management section).

The ILIM pin can also be used to monitor input current when EN_ILIM is enabled. The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 4:

Equation 4. bq25898 bq25898D eq2_IN_slusbu7.gif

For example, if ILIM pin is set with 260-Ω resistor, and the ILIM voltage is 0.4 V, the actual input current 0.557 A - 0.67 A (based on KILM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 0.8 V. If ILIM pin is short, the input current limit is set by the register.

The ILIM pin function can be disabled by setting EN_ILIM bit to 0. When the pin is disabled, both input current limit function and monitoring function are not available.

Thermal Regulation and Thermal Shutdown

Thermal Protection in Buck Mode

The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS.

Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC surface temperature exceeds TSHUT, the boost mode is disabled (converter is turned off) by setting OTG_CONFIG bit low and BATFET is turned off. When IC surface temperature is below TSHUT_HYS, the BATFET is enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

Voltage and Current Monitoring in Buck and Boost Mode

Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck and boost mode operations.

Input Overvoltage (ACOV)

The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT is asserted to the host.

System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to clamp the overshoot.

Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode operation.

VBUS Overcurrent Protection

The charger device closely monitors the RBFET (Q1), and LSFET (Q3) current to ensure safe boost mode operation. During overcurrent condition when output current exceed (IOTG_OCP) the device operates in hiccup mode for protection. While in hiccup mode cycle, the device turns off RBFET for tOTG_OCP_OFF (30 ms typical) and turns on RBFET for tOTG_OCP_ON (250 µs typical) in an attempt to restart. If the overcurrent condition is removed, the boost converter returns to normal operation. When overcurrent condition continues to exist, the device repeats the hiccup cycle until overcurrent condition is removed. When overcurrent condition is detected the fault register bit BOOST_FAULT is set high to indicate fault in boost operation. An INT is also asserted to the host.

Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage protection which stops switching, clears OTG_CONFIG bit and exits boost mode. During the overvoltage duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to the host.

Battery Protection

Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.

Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV.

System Overcurrent Protection

When the system is shorted or significantly overloaded (IBAT > IBATOP) so that its current exceeds the overcurrent limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off condition and turn on BATFET.

Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14) returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the positive supply voltage via a current source or pull-up resistor.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

bq25898 bq25898D Bit_Transfer_on_the_I2C_Bus_SLUSAW5.gif Figure 19. Bit Transfer on the I2C Bus

START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

bq25898 bq25898D START_STOP_conditions_slusbu7.gif Figure 20. START and STOP conditions

Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

bq25898 bq25898D Data_tranfer_I2C_Bus_slusbu7.gif Figure 21. Data Transfer on the I2C Bus

Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

bq25898 bq25898D Complete_data_tranfer_slusbu7.gif Figure 22. Complete Data Transfer

Single Read and Write

bq25898 bq25898D Single_Write_SLUSAW5.gif Figure 23. Single Write
bq25898 bq25898D Single_Read_SLUSAW5.gif Figure 24. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.

bq25898 bq25898D Multi_write_slusbu7.gif Figure 25. Multi-Write
bq25898 bq25898D Multi_read_slusbu7.gif Figure 26. Multi-Read

REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and multi-write.

Device Functional Modes

Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode, WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default settings.

In default mode, the device keeps charging the battery with 12-hour fast charging safety timer. At the end of the 12-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write command to device transitions the charger from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits=00.

When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all registers are reset to default values except IINLIM, VINDPM, VINDPM_OS, BATFET_RST_EN, BATFET_DLY, and BATFET_DIS bits.

bq25898 bq25898D Wathdog_timer_flowchart_slusbu7.gif Figure 27. Watchdog Timer Flow Chart

Register Map

I2C Slave Address: 6AH (1101010B + R/W) (bq25898D)

I2C Slave Address: 6BH (1101011B + R/W) (bq25898)

REG00

Figure 28. REG00
7 6 5 4 3 2 1 0
0 1 0 0 1 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. REG00

Bit Field Type Reset Description
7 EN_HIZ R/W by REG_RST
by Watchdog
Enable HIZ Mode
0 – Disable (default)
1 – Enable
6 EN_ILIM R/W by REG_RST
by Watchdog
Enable ILIM Pin
0 – Disable
1 – Enable (default: Enable ILIM pin (1))
5 IINLIM[5] R/W by REG_RST 1600mA Input Current Limit bq25898D
USB Host SDP = 500mA
USB CDP = 1.5A
USB DCP = 3.25A
Adjustable High Voltage (MaxCharge) DCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2A/2.1A/2.4A

bq25898
PSEL= Hi (USB500) = 500mA
PSEL= Lo = 3.25A
4 IINLIM[4] R/W by REG_RST 800mA
3 IINLIM[3] R/W by REG_RST 400mA
2 IINLIM[2] R/W by REG_RST 200mA
1 IINLIM[1] R/W by REG_RST 100mA
0 IINLIM[0] R/W by REG_RST 50mA

REG01

Figure 29. REG01
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. REG01

Bit Field Type Reset Description
7 DPLUS_DAC[2] R/W by Software D+ Output Driver (default 000)
000 – HiZ
001 – 0V
010 – 0.6V
011 – 1.2V
100 – 2.0V
101 – 2.7V
110 – 3.3V
111 – D+/D- Short (D+ and D- driver are disabled)
6 DPLUS_DAC[1] R/W by Software
5 DPLUS_DAC[0] R/W by Software
4 DMINUS_DAC[2] R/W by Software D- Output Driver (default 000)
000 – HiZ
001 – 0V
010 – 0.6V
011 – 1.2V
100 – 2.0V
101 – 2.7V
110 or 111 – 3.3V
3 DMINUS_DAC[1] R/W by Software
2 DMINUS_DAC[0] R/W by Software
1 EN_12V R/W by Software 0 – Disable 12V for MaxCharge and HVDCP (default)
1 – Enable 12V for MaxCharge and HVDCP
0 VDPM_OS[0] R/W by Software 0 – 400mA offset
1 – 600mA offset (default)

REG02

Figure 30. REG02
7 6 5 4 3 2 1 0
0 0 0 1 1 1 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. REG02

Bit Field Type Reset Description
7 CONV_START R/W by REG_RST
by Watchdog
ADC Conversion Start Control
0 – ADC conversion not active (default).
1 – Start ADC Conversion
This bit is read-only when CONV_RATE = 1. The bit stays high during ADC conversion and during input source detection.
6 CONV_RATE R/W by REG_RST
by Watchdog
ADC Conversion Rate Selection
0 – One shot ADC conversion (default)
1 – Start 1s Continuous Conversion
5 BOOST_FREQ R/W by REG_RST
by Watchdog
Boost Mode Frequency Selection
0 – 1.5MHz (default)
1 – 500KHz
Note: Write to this bit is ignored when OTG_CONFIG is enabled.
4 ICO_EN R/W by REG_RST Input Current Optimizer (ICO) Enable
0 – Disable ICO Algorithm
1 – Enable ICO Algorithm (default)
3 HVDCP_EN R/W by REG_RST High Voltage DCP Enable (bq25898D only)
0 – Disable HVDCP handshake
1 – Enable HVDCP handshake (default)
2 MAXC_EN R/W by REG_RST MaxCharge Adapter Enable (bq25898D only)
0 – Disable MaxCharge handshake
1 – Enable MaxCharge handshake (default)
1 FORCE_DPDM R/W by REG_RST
by Watchdog
Force D+/D- Detection
0 – Not in D+/D- or PSEL detection (default)
1 – Force D+/D- detection
0 AUTO_DPDM_EN R/W by REG_RST Automatic D+/D- Detection Enable
0 –Disable D+/D- or PSEL detection when VBUS is plugged-in
1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default)

REG03

Figure 31. REG03
7 6 5 4 3 2 1 0
0 0 0 1 1 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. REG03

Bit Field Type Reset Description
7 VOK_OTG_EN (bq25898 only) R/W by Software 0 – Disabled, VOK = 0 (default)
1 – Enabled, VOK = 1
1. Adapter Plug-in VOK_OTG_EN = x and VOK = 1
2. OTG if VOK_OTG_EN = 1 ≥ VOK = 1 if VOK_OTG_EN = 0 ≥ VOK = 0
3. Battery Only (non-OTG) VOK_OTG_EN = x and VOK = 0
FORCE_DSEL (bq25898D only) R/W by Software 0 – Allow DSEL = 0 (default)
1 – Force DSEL = 1
1. Adaptor Plug-in DSEL= 1 when:
1) During AUTO_DPDM, FORCE_DPDM, DCP, HVDCP, MaxCharge and FORCE_DSEL = x
or
2) Other input source and FORCE_DSEL = 1 DSEL = 0 when other input source and FORCE_DSEL = 0
2. OTG if FORCE_DSEL = 1 ≥ DSEL = 1 if FORCE_DSEL = 0 ≥ DSEL = 0
3. Battery only (non-OTG) DSEL = 0 and FORCE_DSEL = x
6 WD_RST R/W by Software
by Watchdog
I2C Watchdog Timer Reset
0 – Normal (default)
1 – Reset (Back to 0 after timer reset)
Charger Configuration
5 OTG_CONFIG R/W by REG_RST
by Watchdog
Boost (OTG) Mode Configuration
0 – OTG Disable (default)
1 – OTG Enable
4 CHG_CONFIG R/W by REG_RST
by Watchdog
Charge Enable Configuration
0 - Charge Disable
1- Charge Enable (default)
Minimum System Voltage Limit
3 SYS_MIN[2] R/W by REG_RST 0.4V Minimum System Voltage Limit
Offset: 3.0V
Range 3.0V-3.7V
Default: 3.5V (101)
2 SYS_MIN[1] R/W by REG_RST 0.2V
1 SYS_MIN[0] R/W by REG_RST 0.1V
0 MIN_VBAT_SEL R/W by REG_RST 0 – 2.9V BAT falling (default = 0)
1 – 2.5V BAT falling

REG04

Figure 32. REG04
7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. REG04

Bit Field Type Reset Description
7 EN_PUMPX R/W by REG_RST
by Watchdog
Current pulse control Enable
0 - Disable Current pulse control (default)
1- Enable Current pulse control (PUMPX_UP and PUMPX_DN)
6 ICHG[6] R/W by REG_RST
by Watchdog
4096mA Fast Charge Current Limit
Offset: 0mA
Range: 0mA (0000000) – 4032mA (011111) Default: 2048mA (0100000)
Note:
ICHG=000000 (0mA) disables charge
ICHG > 011111 (4032mA) is clamped to register value 011111 (4032mA)
5 ICHG[5] R/W by REG_RST
by Watchdog
2048mA
4 ICHG[4] R/W by REG_RST
by Watchdog
1024mA
3 ICHG[3] R/W by REG_RST
by Watchdog
512mA
2 ICHG[2] R/W by REG_RST
by Watchdog
256mA
1 ICHG[1] R/W by REG_RST
by Watchdog
128mA
0 ICHG[0] R/W by REG_RST
by Watchdog
64mA

REG05

Figure 33. REG05
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. REG05

Bit Field Type Reset Description
7 IPRECHG[3] R/W by REG_RST
by Watchdog
512mA Precharge Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 0mA when REG04[5:0] = 000000
6 IPRECHG[2] R/W by REG_RST
by Watchdog
256mA
5 IPRECHG[1] R/W by REG_RST
by Watchdog
128mA
4 IPRECHG[0] R/W by REG_RST
by Watchdog
64mA
3 ITERM[3] R/W by REG_RST
by Watchdog
512mA Termination Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 256mA (0011)
2 ITERM[2] R/W by REG_RST
by Watchdog
256mA
1 ITERM[1] R/W by REG_RST
by Watchdog
128mA
0 ITERM[0] R/W by REG_RST
by Watchdog
64mA

REG06

Figure 34. REG06
7 6 5 4 3 2 1 0
0 1 0 1 1 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. REG06

Bit Field Type Reset Description
7 VREG[5] R/W by REG_RST
by Watchdog
512mV Charge Voltage Limit
Offset: 3.840V
Range: 3.840V – 4.608V (110000)
Default: 4.208V (010111)
Note:
VREG > 110000 (4.608V) is clamped to register value 110000 (4.608V)
6 VREG[4] R/W by REG_RST
by Watchdog
256mV
5 VREG[3] R/W by REG_RST
by Watchdog
128mV
4 VREG[2] R/W by REG_RST
by Watchdog
64mV
3 VREG[1] R/W by REG_RST
by Watchdog
32mV
2 VREG[0] R/W by REG_RST
by Watchdog
16mV
1 BATLOWV R/W by REG_RST
by Watchdog
Battery Precharge to Fast Charge Threshold
0 – 2.8V
1 – 3.0V (default)
0 VRECHG R/W by REG_RST
by Watchdog
Battery Recharge Threshold Offset
(below Charge Voltage Limit)
0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])

REG07

Figure 35. REG07
7 6 5 4 3 2 1 0
1 0 0 1 1 1 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. REG07

Bit Field Type Reset Description
7 EN_TERM R/W by REG_RST
by Watchdog
Charging Termination Enable
0 – Disable
1 – Enable (default)
6 STAT_DIS R/W by REG_RST
by Watchdog
STAT Pin Disable
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
5 WATCHDOG[1] R/W by REG_RST
by Watchdog
I2C Watchdog Timer Setting
00 – Disable watchdog timer
01 – 40s (default)
10 – 80s
11 – 160s
4 WATCHDOG[0] R/W by REG_RST
by Watchdog
3 EN_TIMER R/W by REG_RST
by Watchdog
Charging Safety Timer Enable
0 – Disable
1 – Enable (default)
2 CHG_TIMER[1] R/W by REG_RST
by Watchdog
Fast Charge Timer Setting
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (default)
11 – 20 hrs
1 CHG_TIMER[0] R/W by REG_RST
by Watchdog
0 JEITA_ISET (0C-10C) R/W by REG_RST
by Watchdog
JEITA Low Temperature Current Setting
0 – 50% of ICHG (REG04[6:0])
1 – 20% of ICHG (REG04[6:0]) (default)

REG08

Figure 36. REG08
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. REG08

Bit Field Type Reset Description
7 BAT_COMP[2] R/W by REG_RST
by Watchdog
80mΩ IR Compensation Resistor Setting
Range: 0 – 140mΩ
Default: 0Ω (000) (i.e. Disable IRComp)
6 BAT_COMP[1] R/W by REG_RST
by Watchdog
40mΩ
5 BAT_COMP[0] R/W by REG_RST
by Watchdog
20mΩ
4 VCLAMP[2] R/W by REG_RST
by Watchdog
128mV IR Compensation Voltage Clamp
above VREG (REG06[7:2])
Offset: 0mV
Range: 0-224mV
Default: 0mV (000)
3 VCLAMP[1] R/W by REG_RST
by Watchdog
64mV
2 VCLAMP[0] R/W by REG_RST
by Watchdog
32mV
1 TREG[1] R/W by REG_RST
by Watchdog
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (default)
0 TREG[0] R/W by REG_RST
by Watchdog

REG09

Figure 37. REG09
7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. REG09

Bit Field Type Reset Description
7 FORCE_ICO R/W by REG_RST
by Watchdog
Force Start Input Current Optimizer (ICO)
0 – Do not force ICO (default)
1 – Force ICO
Note:
This bit is can only be set only and always returns to 0 after ICO starts
6 TMR2X_EN R/W by REG_RST
by Watchdog
Safety Timer Setting during DPM or Thermal Regulation
0 – Safety timer not slowed by 2X during input DPM or thermal regulation
1 – Safety timer slowed by 2X during input DPM or thermal regulation (default)
5 BATFET_DIS R/W by REG_RST Force BATFET off to enable ship mode with tSM_DLY delay time
0 – Allow BATFET turn on (default)
1 – Force BATFET off
4 JEITA_VSET (45C-60C) R/W by REG_RST
by Watchdog
JEITA High Temperature Voltage Setting
0 – Set Charge Voltage to VREG-200mV during JEITA hig temperature (default)
1 – Set Charge Voltage to VREG during JEITA high temperature
3 BATFET_DLY R/W by REG_RST BATFET turn off delay control
0 – BATFET turn off immediately when BATFET_DIS bit is set (default)
1 – BATFET turn off delay by tSM_DLY when BATFET_DIS bit is set
2 BATFET_RST_EN R/W by REG_RST BATFET full system reset enable
0 – Disable BATFET full system reset
1 – Enable BATFET full system reset (default)
1 PUMPX_UP R/W by REG_RST
by Watchdog
Current pulse control voltage up enable
0 – Disable (default)
1 – Enable
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0 after current pulse control sequence is completed
0 PUMPX_DN R/W by REG_RST
by Watchdog
Current pulse control voltage down enable
0 – Disable (default)
1 – Enable
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0 after current pulse control sequence is completed

REG0A

Figure 38. REG0A
7 6 5 4 3 2 1 0
0 1 1 1 0 1 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. REG0A

Bit Field Type Reset Description
7 BOOSTV[3] R/W by REG_RST
by Watchdog
512mV Boost Voltage Control
Offset: 4.55V
Range: 4.55V – 5.51V
Default:4.998V(0111)
6 BOOSTV[2] R/W by REG_RST
by Watchdog
256mV
5 BOOSTV[1] R/W by REG_RST
by Watchdog
128mV
4 BOOSTV[0] R/W by REG_RST
by Watchdog
64mV
3 PFM_OTG_DIS R/W by REG_RST 0 – Enable (default = 0)
1 – Disable
Boost Current Limit
2 BOOST_LIM[2] R/W by REG_RST
by Watchdog
000: 0.5A
001: 0.8A
010: 1.0A
011: 1.2A
100: 1.5A
101: 1.8A
110: 2.1A
111: 2.4A
Boost Mode Current Limit
Default: 1.5A (100)
1 BOOST_LIM[1] R/W by REG_RST
by Watchdog
0 BOOST_LIM[0] R/W by REG_RST
by Watchdog

REG0B

Figure 39. REG0B
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. REG0B

Bit Field Type Reset Description
7 VBUS_STAT[2] R N/A VBUS Status register
bq25898D
000: No Input 001: USB Host SDP
010: USB CDP (1.5A)
011: USB DCP (3.25A)
100: Adjustable High Voltage DCP (MaxCharge) (1.5A)
101: Unknown Adapter (500mA)
110: Non-Standard Adapter (1A/2A/2.1A/2.4A)
111: OTG
bq25898
000: No Input
001: USB Host SDP
010: Adapter (3.25A)
111: OTG
Note: Software current limit is reported in IINLIM register
6 VBUS_STAT[1] R N/A
5 VBUS_STAT[0] R N/A
4 CHRG_STAT[1] R N/A Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV)
10 – Fast Charging
11 – Charge Termination Done
3 CHRG_STAT[0] R N/A
2 PG_STAT R N/A Power Good Status
0 – Not Power Good
1 – Power Good
1 Reserved R N/A Reserved: Always reads 1
0 VSYS_STAT R N/A VSYS Regulation Status
0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)

REG0C

Figure 40. REG0C
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. REG0C

Bit Field Type Reset Description
7 WATCHDOG_FAULT R N/A Watchdog Fault Status
Status 0 – Normal
1- Watchdog timer expiration
6 BOOST_FAULT R N/A Boost Mode Fault Status
0 – Normal
1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low in boost mode
5 CHRG_FAULT[1] R N/A Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V) )
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
4 CHRG_FAULT[0] R N/A
3 BAT_FAULT R N/A Battery Fault Status
0 – Normal
1 – BATOVP (VBAT > VBATOVP)
2 NTC_FAULT[2] R N/A NTC Fault Status
Buck Mode:
000 – Normal
010 – TS Warm
011 – TS Cool
101 – TS Cold
110 – TS Hot
Boost Mode:
000 – Normal
101 – TS Cold
110 – TS Hot
1 NTC_FAULT[1] R N/A
0 NTC_FAULT[0] R N/A

REG0D

Figure 41. REG0D
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. REG0D

Bit Field Type Reset Description
7 FORCE_VINDPM R/W by REG_RST VINDPM Threshold Setting Method
0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
6 VINDPM[6] R/W by REG_RST 6400mV Absolute VINDPM Threshold
Offset: 2.6V
Range: 3.9V (0001101) – 15.3V (1111111)
Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
Register is read only when FORCE_VINDPM=0 and can be written by internal control based on relative VINDPM threshold setting
Register can be read/write when FORCE_VINDPM = 1
5 VINDPM[5] R/W by REG_RST 3200mV
4 VINDPM[4] R/W by REG_RST 1600mV
3 VINDPM[3] R/W by REG_RST 800mV
2 VINDPM[2] R/W by REG_RST 400mV
1 VINDPM[1] R/W by REG_RST 200mV
0 VINDPM[0] R/W by REG_RST 100mV

REG0E

Figure 42. REG0E
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. REG0E

Bit Field Type Reset Description
7 THERM_STAT R N/A Thermal Regulation Status
0 – Normal
1 – In Thermal Regulation
6 BATV[6] R N/A 1280mV ADC conversion of Battery Voltage (VBAT)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
5 BATV[5] R N/A 640mV
4 BATV[4] R N/A 320mV
3 BATV[3] R N/A 160mV
2 BATV[2] R N/A 80mV
1 BATV[1] R N/A 40mV
0 BATV[0] R N/A 20mV

REG0F

Figure 43. REG0F
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. REG0F

Bit Field Type Reset Description
7 Reserved R N/A Reserved: Always reads 0
6 SYSV[6] R N/A 1280mV ADC conversion of System Voltage (VSYS)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
5 SYSV[5] R N/A 640mV
4 SYSV[4] R N/A 320mV
3 SYSV[3] R N/A 160mV
2 SYSV[2] R N/A 80mV
1 SYSV[1] R N/A 40mV
0 SYSV[0] R N/A 20mV

REG10

Figure 44. REG10
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. REG10

Bit Field Type Reset Description
7 Reserved R N/A Reserved: Always reads 0
6 TSPCT[6] R N/A 29.76% ADC conversion of TS Voltage (TS) as percentage of REGN
Offset: 21%
Range 21% (0000000) – 80% (1111111)
Default: 21% (0000000)
5 TSPCT[5] R N/A 14.88%
4 TSPCT[4] R N/A 7.44%
3 TSPCT[3] R N/A 3.72%
2 TSPCT[2] R N/A 1.86%
1 TSPCT[1] R N/A 0.93%
0 TSPCT[0] R N/A 0.465%

REG11

Figure 45. REG11
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. REG11

Bit Field Type Reset Description
7 VBUS_GD R N/A VBUS Good Status
0 – Not VBUS attached
1 – VBUS Attached
6 VBUSV[6] R N/A 6400mV ADC conversion of VBUS voltage (VBUS)
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
Default: 2.6V (0000000)
5 VBUSV[5] R N/A 3200mV
4 VBUSV[4] R N/A 1600mV
3 VBUSV[3] R N/A 800mV
2 VBUSV[2] R N/A 400mV
1 VBUSV[1] R N/A 200mV
0 VBUSV[0] R N/A 100mV

REG12

Figure 46. REG12
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. REG12

Bit Field Type Reset Description
7 Unused R N/A Always reads 0
6 ICHGR[6] R N/A 3200mA ADC conversion of Charge Current (IBAT) when VBAT > VBATSHORT
Offset: 0mA
Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
Note:
This register returns 0000000 for VBAT < VBATSHORT
5 ICHGR[5] R N/A 1600mA
4 ICHGR[4] R N/A 800mA
3 ICHGR[3] R N/A 400mA
2 ICHGR[2] R N/A 200mA
1 ICHGR[1] R N/A 100mA
0 ICHGR[0] R N/A 50mA

REG13

Figure 47. REG13
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. REG13

Bit Field Type Reset Description
7 VDPM_STAT R N/A VINDPM Status
0 – Not in VINDPM
1 – VINDPM
6 IDPM_STAT R N/A IINDPM Status
0 – Not in IINDPM
1 – IINDPM
5 IDPM_LIM[5] R N/A 1600mA Input Current Limit in effect while Input Current Optimizer (ICO) is enabled
Offset: 100mA (default)
Range 100mA (0000000) – 3.25mA (1111111)
4 IDPM_LIM[4] R N/A 800mA
3 IDPM_LIM[3] R N/A 400mA
2 IDPM_LIM[2] R N/A 200mA
1 IDPM_LIM[1] R N/A 100mA
0 IDPM_LIM[0] R N/A 50mA

REG14

Figure 48. REG14
7 6 5 4 3 2 1 0
0 0 X X X 1 0 1
R/W R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. REG14

Bit Field Type Reset Description
7 REG_RST R/W N/A Register Reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
6 ICO_OPTIMIZED R N/A Input Current Optimizer (ICO) Status
0 – Optimization is in progress
1 – Maximum Input Current Detected
5 PN[2] R N/A Device Configuration
010: bq25898D
000: bq25898
4 PN[1] R N/A
3 PN[0] R N/A
2 TS_PROFILE R N/A Temperature Profile
1- JEITA (default)
1 DEV_REV[1] R N/A Device Revision: 01
0 DEV_REV[0] R N/A