ZHCSDO3C August   2014  – December 2016

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Only
      2. 8.3.2  Adapter Detect and ACOK Output
        1. 8.3.2.1 Adapter Overvoltage (ACOVP)
      3. 8.3.3  System Power Selection
      4. 8.3.4  System Power Up
        1. 8.3.4.1 Dynamic Power Management (IDPM) and Supplement Mode
        2. 8.3.4.2 Minimum System Voltage Regulation and LDO Mode
      5. 8.3.5  Current and Power Monitor
        1. 8.3.5.1 High Accuracy Current Sense Amplifier (IADP and IBAT)
        2. 8.3.5.2 High Accuracey Power Sense Amplifier (PMON)
      6. 8.3.6  Processor Hot Indication for CPU Throttling
      7. 8.3.7  Converter Operation
        1. 8.3.7.1 Continuous Conduction Mode (CCM)
        2. 8.3.7.2 Discontinuous Conduction Mode (DCM)
        3. 8.3.7.3 PFM Mode
        4. 8.3.7.4 Switching Frequency Adjust
      8. 8.3.8  Learn Mode
      9. 8.3.9  Charger Timeout
      10. 8.3.10 Device Protection Features
        1. 8.3.10.1 Input Overcurrent Protection (ACOC)
        2. 8.3.10.2 Converter Overcurrent Protection
        3. 8.3.10.3 Battery Overvoltage Protection (BATOVP)
        4. 8.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.10.5 Thermal Shutdown Protection (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Battery Charging
      2. 8.4.2 System Voltage Regulation with Narrow VDC Architecture
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
      2. 8.5.2 I2C Serial Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 START and STOP Conditions
        3. 8.5.2.3 Byte Format
        4. 8.5.2.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.2.5 Slave Address and Data Direction Bit
        6. 8.5.2.6 Single Read and Write
        7. 8.5.2.7 Multi-Read and Multi-Write
    6. 8.6 Register Maps
      1. 8.6.1 ChargeOption0 Register
      2. 8.6.2 ChargeOption1 Register
      3. 8.6.3 ChargeOption2 Register
      4. 8.6.4 ProchotOption0 Register
      5. 8.6.5 ProchotOption1 Register
      6. 8.6.6 Setting the Charge Current
      7. 8.6.7 Setting the Maximum Charge Voltage
      8. 8.6.8 Setting the Minimum Charge Voltage
      9. 8.6.9 Setting Input Current
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, bq24770
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reverse Input Voltage Protection
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
        6. 9.2.2.6 Input Filter Design
      3. 9.2.3 Application Curves
      4. 9.2.4 Typical Application, bq24773
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The bq2477x is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources from 4.5V to 24V, and 1-4 cell battery for a versatile solution.

The bq2477x supports automatic system power source selection with separate drivers for n-channel MOSFETs on the adapter side, and p-channel MOSFETs on the battery side.

The bq2477x features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the bq2477x supports NVDC architecture to allow battery discharge energy to supplement system power. For details, refer to the System Voltage Regulation with Narrow VDC Architecture section.

The bq2477x closely monitors system power (PMON), input current (IADP) and battery current (IBAT) with highly accurate current sense amplifiers. If current is too high, adapter or battery is removed, a PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the system.

The SMBus/I2C controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.

Functional Block Diagram

bq24770 bq24773 bq24770_FBD_slusc03.gif

Feature Description

Battery Only

Battery is connected to VCC via diode. When VCC voltage is above UVLO, bq2477x powers up to turn on BATFET and starts SMBus/I2C communication. By default, bq2477x stays in low power mode (0x12[15] = 1) with lowest quiescent current.

When 0x12[15] is set to 0, the device enters performance mode. The user can enable IBAT buffer through SMBus/I2C. In order to enable PMON, PROCHOT or independent comparator, the bq2477x enables REGN LDO for accurate reference.

Adapter Detect and ACOK Output

An external resistor divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage. When ACDET is above 0.6V, REGN LDO and bias circuits are enabled.

The open drain ACOK output can be pulled to external rail under the following conditions:

  • V(UVLO) < V(VCC) < V(ACOVP)
  • V(ACDET) > 2.4 V
  • V(VCC) – V(SRN) > V(VCC_SRN_RISE)

Adapter Overvoltage (ACOVP)

When the VCC pin voltage is higher than 26 V, it is considered adapter over voltage. ACOK is pulled low, and charge is disabled. ACFET/RBFET are turned off to disconnect the high voltage adapter to system during ACOVP. BATFET is turned on if turn-on conditions are valid. When VCC voltage falls below 22 V, it is considered as adapter voltage returns back to normal voltage. ACOK is pulled high by an external pullup resistor. BATFET is turned off and ACFET and RBFET is turned on to power the system from the adapter.

System Power Selection

The bq2477x device automatically switches adapter or battery power to system.

The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET) between adapter and ACP (see Figure 21 for details). The ACFET separates adapter from system and battery, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. The RBFET provides negative input voltage protection and battery discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode.

When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting the adapter from the system. BATDRV stays as low as VSRN – 10 V to connect battery to system if all of the following conditions are valid:

  • V(VCC) > V(UVLO)
  • V(SRN) – V(SRP) > 2.56 mV

After the adapter plugs in, the system power source switches from battery to adapter if ACOK is HIGH. The gate drive voltage on ACFET and RBFET is V(CMSRC) + 6 V. If ACDRV-CMSRC voltage drops at least 100 mV from its normal voltage, the converter stops.

To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be carefully selected following the guidelines below:

  • Minimize total capacitance on system
  • Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in
  • Check with MOSFET vendor on peak current rating
  • Place 4 kΩ resistor in series with ACDRV and CMSRC pins to limit MOSFET turn on/off time.

System Power Up

After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck output current to avoid any overshoot or stress on the output capacitors or the power converter. No external components are needed for this function.

When power up, the converter output voltage is a default value set by CELL pin configuration.

Table 1. Cell Pin Configuration

CELL PIN DEFAULT BATTERY CONFIGURATION DEFAULT
MaxChargevoltage()
DEFAULT
MinSystemVoltage()
SYSOVP
THRESHOLD
Low 1s 4400mV 3568mV 5 V
Float 2s 9008mV 6144mV 12 V
High 3s/4s 13504mV 9008mV 18.5 V when
MaxChargeVoltage() < 15 V

Dynamic Power Management (IDPM) and Supplement Mode

When the input current exceeds the input current setting, the bq2477x decreases the charge current to provide priority to system load. As the system current rises, the available charge current drops accordingly toward zero. If the system load keeps increasing after charge current drops down to zero, the system voltage starts to drop. As the system voltage drops below battery voltage, the device enters supplement mode, the battery starts discharge, and the total system power equals to input supply power and battery discharge power.

Minimum System Voltage Regulation and LDO Mode

The BATDRV drives a p-channel BATFET between converter output and battery to provide a charge and discharge path for battery. The system is always above the MinSystemVoltage() even with depleted battery or without battery.

When battery voltage is below the minimum system voltage setting, this BATFET works in linear mode (LDO mode) during battery charging. The precharge current is set by ChargeCurrent() and clamped below 384mA. If battery voltage reaches the minimum system voltage, BATFET fully turns on.

The minimum BATDRV voltage is 1.1 V. For 1s application, the BATFET has to fully turn on when the gate voltage is 1.1 V or higher. Otherwise, BATFET may not operate properly.

Current and Power Monitor

High Accuracy Current Sense Amplifier (IADP and IBAT)

As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current (IADP) and the charge/discharge current (IBAT). IADP voltage is 40X or 80X the differential voltage across ACP and ACN. IBAT voltage is 20X (during charging), or 8X/16X (during discharging) of the differential across SRP and SRN. After VCC is above V(UVLO) and ACDET is above 0.6 V, IADP output becomes valid. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved.

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V.

High Accuracey Power Sense Amplifier (PMON)

The bq2477x device monitors total available power from adapter and battery together. The ratio of PMON current and total power K(PMON) can be programmed in ChargeOption1() bit[8] with default 1µA/W. The bq2477x device allows input sense resistor 2× of charge sense resistor by setting ChargeOption1() bit[12] to 1.

Equation 1. I = K(PMON)(VIN × IIN + VBAT × IBAT ) (IBAT > 0 during battery discharging, IBAT < 0 during battery charging) )

A maximum PMON output current is 100µA. The user picks output resistor based on peak system power rating. The PMON output voltage is clamped below 3.3V.

Processor Hot Indication for CPU Throttling

When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery. The adapter current and battery discharge overshoot, or system voltage drop indicates the system power may be too high. When the adapter or battery is removed, the remaining power source may not support the peak power in turbo mode. The processor hot function in bq2477x monitors these events, and PROCHOT pulse is asserted.

The PROCHOT triggering events include:

  • ICRIT: adapter peak current
  • INOM: adapter average current (110% of input current limit)
  • IDCHG: battery discharge current
  • VSYS: system voltage on SRN for 2s - 4s battery
  • ACOK: upon adapter removal (ACOK pin HIGH to LOW)
  • BATPRES: upon battery removal (BATPRES pin LOW to HIGH)
  • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0].

bq24770 bq24773 fbd_prochot_profile_slusc03.gif Figure 5. PROCHOT Profile

When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms (default 0x3C[4:3]). At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

Converter Operation

The bq2477x typically use 2.2/3.3 µH inductor and 60 µF output capacitance to achieve all loops stable. This capacitance could be from system bus decoupling cap. But in order to achieve good output transient response, like mini output drop or min output spike, then it is better to have more output capacitance from the system bus, which could be the total input capacitance from the input of the down-stream DC-DC converters for CPU core, DDR and chip-set.

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a DC bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value to get the required value at the operating point.

Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current does not cross 0, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and lowside MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low and allows safe charging at high currents.

Discontinuous Conduction Mode (DCM)

During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to 0, the converter enters DCM. Every cycle, when the voltage across SRP and SRN falls below 0 mV, the undercurrent-protection comparator (UCP) turns off LSFET to avoid negative inductor current, which may boost the system through the body diode of HSFET.

During DCM the loop response automatically changes. It changes to a single-pole system and the pole is proportional to the load current.

PFM Mode

In order to improve converter light-load efficiency, the bq2477x switches to PFM control at light load with charge disable or charge in LDO mode. The effective switching frequency will decrease accordingly when system load decreases. The minimum frequency can be limit to 40kHz (ChargeOption0() bit[10]=1). To have higher light load efficiency, set "Audio Frequency Limit" bit low (Chargeoption0() bit[10]=0).

Switching Frequency Adjust

The charger switching frequency can be adjusted to solve EMI issue via SMBus/I2C command. ChargeOption0() bit [9:8] can be used to set switching frequency. If frequency is reduced, the current ripple is increased. Inductor value must be carefully selected so that it will not trigger cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency.

Learn Mode

LEARN mode is set up to calibrate gauge in the pack. When LEARN is enabled, the system first discharge the battery below depletion threshold, and complete another charging cycle for gauge calibration. During the discharging, BATFET turns on and converter stops.

A battery LEARN cycle can be activated via SMBus/I2C "LEARN Enable" command (ChargeOption0() bit[5]=1 enable Learn Mode). When LEARN is enabled with an adapter connected, the system power switch to battery by turning off converter and keep ACFET/BATFET on. Learn mode allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. When LEARN is disabled, the system power switch to adapter by turning on converter in a few hundreds μs.

bq2477x also supports hardware pin to exist LEARN mode by driving BATPRES to HIGH. When BATPRES pin is pulled to HIGH, bq2477x resets "LEARN Enable" (ChargeOption0() bit[5]) and IDPM_EN (ChargeOption() bit[1]), and reset MaxChargeVoltage() and ChargeCurrent().

Charger Timeout

The bq2477x includes a watchdog timer to terminate charging if the charger does not receive a write MaxChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). If watchdog is in timeout, disabling watchdog timer by writing ChargeOption() bit[14:13] also resumes charging.

Device Protection Features

Input Overcurrent Protection (ACOC)

If the input current exceeds the 3X of input current DAC set point, the converter is disabled. After 300ms, the converter is turned on again.

The ACOC function threshold can be set to 3X of input DPM current (ChargeOption0 bit [7]=1) or function disable (ChargeOption0) bit [7]=0, default) via SMBus command The bq2477x has a cycle-to-cycle peak overcurrent protection. It monitors the voltage across Rds(on) of the LSFET or the input current sense resistor, and prevents the converter from over current condition. The high-side gate drive turns off when the overcurrent is detected, and resumes automatically when the overcurrent condition is gone.

Converter Overcurrent Protection

When LODRV pulse is longer than 100ns, the LSFET OCP is active and the threshold is automatically set to 290mV (ChargeOption0() bit [6]=1, default) or 170mV (ChargeOption0() bit [6]=0) via SMBus/I2C command. The blanking time prevents noise when MOSFET just turn on.

When LODRV pulse is shorter than 100ns, bq2477x sets OCP limit proportional to PROCHOT ICRIT setting (ProchotOption0() bit[8]). The IDPM function is disabled (0x12[1]=0). Set InputCurrent() to a right value even IDPM is disabled.

Battery Overvoltage Protection (BATOVP)

The bq2477x immediately stops the converter when the voltage at BAT exceeds 104% (1s) or 102% (2s – 4s) of the regulation voltage set-point. This allows quick response to an overvoltage condition – such as occurs when the load is removed or the battery is disconnected. A 19 mA current sink from SRP/SRN to GND is on only during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors.

System Overvoltage Protection (SYSOVP)

When the converter starts up, the bq24770 reads CELL pin configuration and sets MaxChargeVoltage() and SYSOVP threshold (1s – 5 V, 2s – 12 V, 3s – 18.5 V). Before MaxChargeVoltage() is written by host, the battery configuration will change with CELL pin voltage.

When SYSOVP happens, the device latchs off ACFET/RBFET. Register ChargeOption0() bit[12] is set as 1.

The user can clear the latch off by either write of 0 to register bit or removal and plugin adapter again (ACDET below 0.6V and back up again). After the latch-off is cleared, ACFET/RBFET turn on and converter starts.

Thermal Shutdown Protection (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shutdown, the REGN LDO current limit is reduced to 14 mA.

Once the temperature falls below 135°C, charge can be resumed with soft start.

Device Functional Modes

Battery Charging

The bq2477x charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. The host programs battery voltage to ChargeVoltage() (0x15()). According to battery voltage, the host programs appropriate charge current to ChargeCurrent() (0x14()). When battery is full or battery is not in good condition to charge, host terminates charge by setting 0x12[0] to 1, or setting ChargeCurrent() to zero.

See the Feature Description section for details on charge enable conditions and register programming.

System Voltage Regulation with Narrow VDC Architecture

The bq2477x deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode). As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

See the Feature Description section for details on system voltage regulation and register programming.

Programming

SMBus Interface

The bq24770 device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24770 device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24770 device uses the SMBus read-word and write-word protocols (shown in Table 2 and Table 3) to communicate with the smart battery. The bq24770 device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the bq24770 device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus/I2C communication starts when VCC is above V(UVLO).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 6 and Figure 7 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq2477x device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq2477x supports the charger commands listed in Table 2.

SMBus Write-Word and Read-Word Protocols

Table 2. Write-Word Format

S
(1)(3)
SLAVE ADDRESS(1) W
(1)(6)
ACK
(2)(5)
COMMAND BYTE(1) ACK
(2)(5)
LOW DATA BYTE(1) ACK
(2)(5)
HIGH DATA BYTE(1) ACK
(2)(5)
P
(1)(4)
7 bits 1b 1b 8 bits 1b 8 bits 1b 8 bits 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0
Master to slave
Slave to master (shaded gray)
S = Start condition or repeated start condition
P = Stop condition
ACK = Acknowledge (logic-low)
W = Write bit (logic-low)

Table 3. Read-Word Format

S(1)(3) SLAVE ADDRESS(1) W
(1)(7)
ACK
(2)(5)
COMMAND BYTE(1) ACK
(2)(5)
S(1)(3) SLAVE ADDRESS(1) R(1)(8) ACK
(2)(5)
LOW DATA BYTE(2) ACK
(1)(5)
HIGH DATA BYTE(2) NACK
(1)(6)
P
(1)(4)
7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits 1b 8 bits 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1
Master to slave
Slave to master (shaded gray)
S = Start condition or repeated start condition
P = Stop condition
ACK = Acknowledge (logic-low)
NACK = Not acknowledge (logic-high)
W = Write bit (logic-low)
R = Read bit (logic-high)

Timing Diagrams

bq24770 bq24773 timing_write_SLUSBW0.gif
A = Start condition H = LSB of data clocked into slave
B = MSB of address clocked into slave I = Slave pulls SMBDATA line low
C = LSB of address clocked into slave J = Acknowledge clocked into master
D = R/W bit clocked into slave K = Acknowledge clock pulse
E = Slave pulls SMBDATA line low L = Stop condition, data executed by slave
F = ACKNOWLEDGE bit clocked into master M = New start condition
G = MSB of data clocked into slave
Figure 6. SMBus Write Timing
bq24770 bq24773 timing_read_SLUSBW0.gif
A = Start condition G = MSB of data clocked into master
B = MSB of address clocked into slave H = LSB of data clocked into master
C = LSB of address clocked into slave I = Acknowledge clock pulse
D = R/W bit clocked into slave J = Stop condition
E = Slave pulls SMBDATA line low K = New start condition
F = ACKNOWLEDGE bit clocked into master
Figure 7. SMBus Read Timing

I2C Serial Interface

The bq24773 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address D4H, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG0F. The I2C interface supports both standard mode (up to 100kbits), and fast mode (up to 400kbits). connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

bq24770 bq24773 Bit_transfer_on_I2C_slusc03.gif Figure 8. Bit Transfer on the I2C Bus

START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

bq24770 bq24773 STARTandSTOP_conditions_slusc03.gif Figure 9. START and STOP Conditions

Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

bq24770 bq24773 Data_transfer_on_I2C_slusc03.gif Figure 10. Data Transfer on the I2C Bus

Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

bq24770 bq24773 complete_data_transfer_slusc03.gif Figure 11. Complete Data Transfer

Single Read and Write

bq24770 bq24773 single_write_slusc03.png Figure 12. Single Write
bq24770 bq24773 single_read_slusc03.png Figure 13. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

Multi-Read and Multi-Write

The charger device supports multi-read and multi-write.

bq24770 bq24773 multi_write_slusc03.png Figure 14. Multi Write
bq24770 bq24773 multi_read_slusc03.png Figure 15. Multi Read

Register Maps

The bq2477x supports battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 4. The SMBUS address is 0x12H or 0001001_X, and I2C address is D4H or 1101010_X, where X is the read/write bit. ManufacturerID() and DeviceID() can be used to identify the bq2477x. The ManufacturerID() command always returns 0x0040H.

Table 4. Battery Charger Command Summary

REGISTER ADDRESS REGISTER NAME R/W DESCRIPTION POR STATE
SMBus: 0x12H
I2C: 01H/00H
ChargeOption0() R/W Charger Option Control 0 0xE14EH
SMBus: 0x3B
I2C: 03H/02H
ChargeOption1() R/W Charge Option Control 1 0x0211H
SMBus: 0x38H
I2C: 11H/10H
ChargeOption2() R/W Charge Options Control 2 0x0080H
SMBus: 0x3CH
I2C: 05H/04H
ProchotOption0() R/W PROCHOT Option 0 0x4B54H
SMBus: 0x3DH
I2C: 07H/06H
ProchotOption1() R/W PROCHOT Option 1 0x8120H
SMBus: 0x14H
I2C: 0BH/0AH
ChargeCurrent() R/W 7-Bit Charge Current Setting 0x0000H
SMBus: 0x15H
I2C: 0DH/0CH
MaxChargeVoltage() R/W 11-Bit Charge Voltage Setting 1S-4.4V, 2S-9.008V, 3S/4S-13.504V
SMBus: 0x3EH
I2C: 0EH
MinSystemVoltage() R/W 6-Bit Minimum System Voltage Setting 1S-3.584V, 2S-6.144V, 3S/4S-9.216V
SMBus: 0x3FH
I2C: 0FH
InputCurrent() R/W 7-Bit Input Current Setting 3200mA (770), 2944mA (773)
SMBus: 0xFEH ManufacturerID() Read Only Manufacturer ID 0x0040H
SMBus: 0xFFH
I2C: 09H
DeviceAddress() Read Only Device Address 0x0114H (770)
0x41H (773)

ChargeOption0 Register

Figure 16. ChargeOption0 Register (0x12H)
15 14 13 12 11 10 9 8
Low Power Mode Enable WATCHDOG Timer Adjust IDPM AUTO DISABLE SYSOVP Status& Clear Audio Frequency Limit Switching Frequency[1:0]
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
ACOC Setting LSFET OCP Threshold LEARN Enable IADP Amplifier Ratio IBAT Amplifier Ratio for Discharge Current Reserved IDPM Enable Charge Inhibit
R/W R/W R/W R/W R/W R R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. ChargeOption0 Register (0x12H)

I2C
01H
I2C
00H
SMBus
0x12H
BIT NAME DESCRIPTION
[7] [15] Low Power Mode Enable 0: IC in performance mode with battery only. The enable of PROCHOT, current monitor buffer, power monitor buffer and comparator follow register setting.
1: IC in low power mode with battery only. IC is in the lowest quiescent current when this bit is enabled. /PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. <default at POR>
[6:5] [14:13] WATCHDOG Timer Adjust Set maximum delay between consecutive SMBus/I2C Write charge voltage or charge current command.
If IC does not receive write on MaxChargeVoltage() or ChargeCurrent() within the watchdog time period, ChargeCurrent() is set to 0mA to stop charging. The converter keeps running to regulate the system voltage.
After expiration, the timer will resume upon the write of MaxChargeVoltage() or ChargeCurrent().
00: Disable Watchdog Timer
01: Enabled, 44 sec
10: Enabled, 88 sec
11: Enable Watchdog Timer (175s) <default at POR>
[4] [12] IDPM AUTO DISABLE When the BATPRES pin goes from LOW to HIGH, the charger IC automatically disables the IDPM function (IDPM Enable bit becomes 0). The host can enable IDPM function again by writing IDPM_EN bit 1.
0 – Disable this function <default at POR>
1 – Enable this function
[3] [11] SYSOVP Status& Clear When the SYSOVP occurs, the bit is HIGH. After the SYSOVP is removed, the user must write a 0 to this register or unplug the adapter to clear the OVP condition.
0: not in SYSOVP, write 0 to clear SYSOVP latch <default at POR>
1: Device in SYSOVP, ACFET/RBFET latches off
[2] [10] Audio Frequency Limit 0: No limit of switching frequency <default at POR>
1: Set minimum switching frequency to 40kHz to avoid audio noise
[1:0] [9:8] Switching Frequency[1:0] Converter switching frequency.
00: 600 kHz
01: 800kHz <default at POR in bq24770>
10: 1 MHz
11: 1.2MHz <default at POR in bq24773>
[7] [7] ACOC Setting Input over-current protection threshold by detecting ACP_ACN voltage.
0: disable ACOC <default at POR>
1: ACOC limit 300% of IDPM
[6] [6] LSFET OCP Threshold Cycle-by-cycle over-current protection threshold by detecting GND-PHASE
0: 170mV
1: 290mV <default at POR>
[5] [5] LEARN Enable Battery LEARN mode enable. In LEARN mode, buck converter turns off while ACFET and RBFET stay on. The BATFET turns on to discharge.
Set this bit 0 will stop LEARN mode and turn back on buck converter.
0: Disable LEARN Mode <default at POR>
1: Enable LEARN Mode
[4] [4] IADP Amplifier Ratio 0: 40x <default at POR>
1: 80x
[3] [3] IBAT Amplifier Ratio for Discharge Current 0: 8x
1: 16x <default at POR>
[2] [2] Reserved 1- Reserved
[1] [1] IDPM Enable Input regulation loop enable.
0 – IDPM disabled
1 – IDPM enabled <default at POR>
[0] [0] Charge Inhibit Change inhibit bit. To enable charge, first writes this bit to 0 and then write 0x14() non-zero value.
0: Enable charge <default at POR>
1: Disable charge

ChargeOption1 Register

Figure 17. ChargeOption1 Register (0x3BH)
15 14 13 12 11 10 9 8
Reserved RSNS_RATIO IBAT Enable PMON Enable PMON Gain Reserved
R R/W R/W R/W R/W R
7 6 5 4 3 2 1 0
CMP_REF CMP_POL CMP_DEG [1:0] FET Latch-off Enable FORCE BATFET Off Discharge BAT Enable Auto Wakeup Enable
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. ChargeOption1 Register (0x3BH)

I2C
03H
I2C
02H
SMBus
0x3BH
BIT NAME DESCRIPTION
[7:5] [15:13] 0- Reserved
[4] [12] RSNS_RATIO Adjust ratio of input sense resistor (RAC) and charge sense resistor (RSR) for power calculation.
0: RAC and RSR 1:1 <default at POR>
1: RAC and RSR 2:1
[3] [11] IBAT Enable Enable the IBAT output buffer.
0: Turn off IBAT buffer to minimize Iq <default at POR>
1: Turn on IBAT buffer
[2] [10] PMON Enable Enable PMON sensing circuit and output buffer.
0: turn off PMON buffer to minimize Iq <default at POR>
1: turn on PMON buffer
[1] [9] PMON Gain PMON output current with respect to the total system power on 10mohm RAC and RSR.
0: 0.25 µA/W
1: 1µA/W <default at POR>
[0] [8] Reserved 0- Reserved
[7] [7] CMP_REF Independent comparator internal reference.
0: 2.3 V <default at POR>
1: 1.2 V
[6] [6] CMP_POL Independent comparator output polarity
0: When CMPIN is above internal threshold, CMPOUT is LOW <default at POR>
1: When CMPIN is above internal threshold, CMPOUT is HIGH
[5:4] [5:4] CMP_DEG [1:0] Independent comparator deglitch time.
00: Independent comparator is disabled
01: Independent comparator is enabled with output deglitch time 2 µs  <default at POR>
10: Independent comparator is enabled with output deglitch time 2 ms
11: Independent comparator is enabled with output deglitch time 5 sec
[3] [3] FET Latch-off Enable When comparator is triggered, all the power path MOSFETs latch off. In order to clear power path latch off, both adapter and battery have to be removed. Therefore, at POR state, the latch off is cleared.
0: When comparator is triggered, no power path latch off <default at POR>
1: When comparator is triggered, power path latches off
[2] [2] FORCE BATFET Off The host can force BATFET to turn off at any time. After BATFET is forced off, plugin adapter will set the bit back to 0.
0: Allow BATFET turn on <default at POR>
1: Turn off BATFET
[1] [1] Discharge BAT Enable When this bit is 1, discharge BAT pin down below 3.8 V in 40 ms. When 40ms is over, this bit is reset to 0.
0 : Disable discharge mode <default at POR>
1: Enable discharge mode
[0] [0] Auto Wakeup Enable When this bit is HIGH, if the battery is below 3 V(1s) or 6 V(2s-4s), the IC will automatically enable 128 mA charging current to charge depleted battery for 30 mins. When the battery voltage exceeds 3 V (1S) or 6 V (2S-4S), the charge will stop after 1min deglitch time.
After the 30 mins expires, the charging will stop, and this bit is set back to LOW.
0: Disable auto-wakeup
1: Enable auto-wakeup <default at POR>

ChargeOption2 Register

Figure 18. ChargeOption2 Register (0x38H)
15 14 13 12 11 10 9 8
Reserved
R
7 6 5 4 3 2 1 0
External ILIM Enable IBAT Output Select Reserved
R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. ChargeOption2 Register (0x38H)

I2C
10H
SMBus
0x38H
BIT NAME DESCRIPTION
[15:8] 0- Reserved
[7] [7] External ILIM Enable 0: Input current limit is set by REG0x3F.
1: Input current limit is set by the lower value of ILIM pin and REG0x3F. <default at POR>
[6] [6] IBAT Output Select 0: IBAT pin as discharge current. <default at POR>
1: IBAT pin as charge current.
[5:0] [5:0] Reserved 0- Reserved

ProchotOption0 Register

Figure 19. ProchotOption0 Register (0x3CH)
15 14 13 12 11 10 9 8
ICRIT Comparator Threshold ICRIT Comparator Deglitch Time Input OCP Threshold
R/W R/W R/W
7 6 5 4 3 2 1 0
VSYS comparator threshold PROCHOT Pulse Extension Enable PROCHOT Pulse Width PROCHOT Host Clear INOM Comparator Deglitch Time Reserved
R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. ProchotOption0 Register (0x3CH)

I2C
05H
I2C
04H
SMBus
0x3CH
BIT NAME DESCRIPTION
[7:3] [15:11] ICRIT Comparator Threshold 5 bits, percentage of IDPM in 0x3FH. Measure current between ACP and ACN. Trigger when the current is above this threshold.
Step: 5%, Default 150% (01001)
00000:110%

11010:250%
11110:450%
00001:110%
10111:220%
11011:300%
11111:Out of Range
00010:115%
11000:225%
11100:350%
00011:120%
11001:230%
11101:400%
If IDPM setting exceeds 3.584A (0111000), ICRIT threshold is clamped at 230%.
[2:1] [10:9] ICRIT Comparator Deglitch Time 00: 10 µs
01: 100 µs <default at POR>
10: 400 µs
11: 800 µs
[0] [8] Input OCP Threshold Input over-current setting by detecting ACP-ACN.
0: 125% of ICRIT
1: 200% of ICRIT <default at POR>
[7:6] [7:6] VSYS comparator threshold Measure on SRP with fixed 20us deglitch time. Trigger when SRP voltage is below the threshold.
00: 5.75 V (2-4s) or 2.85 V (1s)
01: 6V (2-4s) or 3.1V (1s) <default at POR>
10: 6.25 V (2-4s) or 3.3 5V (1s)
11: 6.5 V (2-4s) or 3.6 V (1s)
[5] [5] PROCHOT Pulse Extension Enable When pulse extension is enabled, keep PROCHOT pin voltage low until host writes 0x3C[2]=1.
0: Pulse width is set by REG0x3C[4:3] <default at POR>
1: Pulse stays LOW till host sets REG0x3C[2] to 0.
[4:3] [4:3] PROCHOT Pulse Width Minimum PROCHOT pulse width when REG0x3C[5]=0
00: 100 µs
01: 1 ms
10: 12 ms <default at POR>
11: 6 ms
[2] [2] PROCHOT Host Clear Clear PROCHOT pulse when REG0x3C[5]=1.
0: Clear PROCHOT pulse and drive /PROCHOT pin to HIGH.
1: Idle <default at POR>
[1] [1] INOM Comparator Deglitch Time INOM is always 10% above IDPM in 0x3FH. Measure current between ACP and ACN. Trigger when the current is above this threshold.
0: 1ms max <default at POR>
1: 50 ms max
[0] [0] Reserved 0- Reserved

ProchotOption1 Register

Figure 20. ProchotOption1 Register (0x3DH)
15 14 13 12 11 10 9 8
IDCHG Comparator Threshold IDCHG Comparator Deglitch Time
R/W R/W
7 6 5 4 3 2 1 0
Reserved PROCHOT envelop selector
R R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. ProchotOption1 Register (0x3DH)

I2C
07H
I2C
06H
SMBus
0x3DH
BIT NAME DESCRIPTION
[7:2] [15:10] IDCHG Comparator Threshold 6 bit, range, range  0A – 32256 mA, step 512 mA. Measure current between SRN and SRP. Trigger when the discharge current is above the threshold.
Default: 16384 mA (100000)
[1:0] [9:8] IDCHG Comparator Deglitch Time 00: 1.6 ms
01: 100 µs <default at POR>
10: 6 ms
11: 12 ms
[7] [7] Reserved 0- Reserved
[6:0] [6:0] PROCHOT envelop selector When adapter is present, the /PROCHOT function is enabled by the below bits.
When adapter is removed, ICRIT, INOM, BATPRES and ACOK functions are automatically disabled in the PROCHOT profile. Comparator, IBAT and VSYS function setting are preserved. When all the bits are 0, PROCHOT function is disabled.
Bit6: Independent comparator, 0: disable <default at POR>; 1: enable
Bit5: ICRIT, 0: disable; 1: enable <default at POR>
Bit4: INOM, 0: disable <default at POR>; 1: enable
Bit3: IDCHG, 0: disable <default at POR>; 1: enable
Bit2: VSYS, 0: disable; 1: enable <default at POR>
Bit1: BATPRES, 0: disable <default at POR> ; 1: enable (one-shot rising edge triggered)
Bit0: ACOK, 0: disable <default at POR> ; 1: enable (one-shot falling edge triggered)

Setting the Charge Current

To set the charge current, write a 16-bit ChargeCurrent() command. With 10mΩ sense resistor, the bq2477x provides charge current range of 128mA to 8.128A, with 64mA step resolution. It is suggested to write battery voltage to MaxChargeVoltage() before programming ChargeCurrent(). When battery is absent, the host should write 0A to ChargeCurrent().

During pre-charge, the charge current is clamped at 384mA. Sending ChargeCurrent() 0mA will terminate charge. Upon POR, charge current setting is 0mA.

For 1s charging, the charge current is clamped at 384 mA when battery is below BATLOWV threshold. When battery is between BATLOWV and SYSMIN, the charging current is clamped at 2 A. When battery is above SYSMIN, the charging current follows register setting.

To program charge current in bq24773, the host has to write 2-byte command with REG0A first, followed by REG0B. No other command can be inserted in between. After the completion of REG0A and REG0B, charge current will be updated. If host writes REG0B first, the command will be ignored. If the time between write of REG0A and REG0B exceeds watchdog timer, the REG0A command will be ignored.

The SRP and SRN pins are used to sense voltage drop across RSR with default value of 10mΩ. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but at the expense of higher conduction loss. A current sensing resistor value no more than 20mΩ is suggested.

A 0.1µF capacitor between SRP and SRN for differential mode filtering is recommended; a 0.1µF capacitor between SRN and ground, and an optional 0.1µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1µF in order to properly sense voltage across SRP and SRN.

Table 10. Charge Current Register with 10mΩ Sense Resistor

I2C
0BH
I2C
0AH
SMBus
0x14H
BIT NAME DESCRIPTION
0 0 Not used. Value ignored.
1 1 Not used. Value ignored.
2 2 Not used. Value ignored.
3 3 Not used. Value ignored.
4 4 Not used. Value ignored.
5 5 Not used. Value ignored.
6 6 Charge Current, DACICHG 0 0 = Adds 0mA of charger current.
1 = Adds 64mA of charger current.
7 7 Charge Current, DACICHG 1 0 = Adds 0mA of charger current.
1 = Adds 128mA of charger current.
0 8 Charge Current, DACICHG 2 0 = Adds 0mA of charger current.
1 = Adds 256mA of charger current.
1 9 Charge Current, DACICHG 3 0 = Adds 0mA of charger current.
1 = Adds 512mA of charger current.
2 10 Charge Current, DACICHG 4 0 = Adds 0mA of charger current.
1 = Adds 1024mA of charger current.
3 11 Charge Current, DACICHG 5 0 = Adds 0mA of charger current.
1 = Adds 2048mA of charger current.
4 12 Charge Current, DACICHG 6 0 = Adds 0mA of charger current.
1 = Adds 4096mA of charger current.
5 13 Not used. 1 = invalid write.
6 14 Not used. 1 = invalid write.
7 15 Not used. 1 = invalid write.

Setting the Maximum Charge Voltage

To set the output charge regulation voltage, write a 16-bit MaxChargeVoltage() command. The bq2477x provides charge voltage range from 1.024V to 19.200V, with 16mV step resolution. Upon POR or when charge is disabled, the system is regulated at MaxChargeVoltage().

If enable charge without writing any command to MaxChargeVoltage(), the MaxChargeVoltage() is automatically changed to 4.2V/cell. If disable charge without writing any command to MaxChargeVoltage(), the MaxChargeVoltage() automatically goes back to POR value. Once writing a valid value to MaxChargeVoltage(), the register doesn’t automatically change between charge enable and disable.

The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery pack positive side as possible. A decoupling capacitor of 0.1µF is recommended as close to IC as possible to decouple high frequency noise.

To program charge voltage in bq24773, the host has to write 2-byte command with REG0C first, followed by REG0D. No other command can be inserted in between. After the completion of REG0C and REG0D, charge voltage will be updated. If host writes REG0D first, the command will be ignored. If the time between write of REG0C and REG0D exceeds watchdog timer, the REG0C command will be ignored.

Table 11. Max Charge Voltage Register

I2C
0DH
I2C
0CH
SMBus
REG 0x15H
BIT NAME DESCRIPTION
0 0 Not used. Value ignored.
1 1 Not used. Value ignored.
2 2 Not used. Value ignored.
3 3 Not used. Value ignored.
4 4 Charge Voltage, DACV 0 0 = Adds 0mV of charger voltage.
1 = Adds 16mV of charger voltage.
5 5 Charge Voltage, DACV 1 0 = Adds 0mV of charger voltage.
1 = Adds 32mV of charger voltage.
6 6 Charge Voltage, DACV 2 0 = Adds 0mV of charger voltage.
1 = Adds 64mV of charger voltage.
7 7 Charge Voltage, DACV 3 0 = Adds 0mV of charger voltage.
1 = Adds 128mV of charger voltage.
0 8 Charge Voltage, DACV 4 0 = Adds 0mV of charger voltage.
1 = Adds 256mV of charger voltage.
1 9 Charge Voltage, DACV 5 0 = Adds 0mV of charger voltage.
1 = Adds 512mV of charger voltage.
2 10 Charge Voltage, DACV 6 0 = Adds 0mV of charger voltage.
1 = Adds 1024mV of charger voltage.
3 11 Charge Voltage, DACV 7 0 = Adds 0mV of charger voltage.
1 = Adds 2048mV of charger voltage.
4 12 Charge Voltage, DACV 8 0 = Adds 0mV of charger voltage.
1 = Adds 4096mV of charger voltage.
5 13 Charge Voltage, DACV 9 0 = Adds 0mV of charger voltage.
1 = Adds 8192mV of charger voltage.
6 14 Charge Voltage, DACV 10 0 = Adds 0mV of charger voltage.
1 = Adds 16384mV of charger voltage.
7 15 Not used. 1 = invalid write.

Setting the Minimum Charge Voltage

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. When charge is enabled, and the battery is below MinSystemVoltage(), the system is regulated at the minimum system voltage setting. When charge is disabled, the system is regulated at MaxChargeVoltage().

To set the minimum system voltage, write a 16-bit MinSystemVoltage() command. The bq2477x provides minimum system voltage range from 1.024V to 19.200V, with 256mV step resolution.

Table 12. Minimum System Voltage Register

I2C
0EH
SMBus
0x3EH
BIT NAME DESCRIPTION
0 Not used. Value ignored.
1 Not used. Value ignored.
2 Not used. Value ignored.
3 Not used. Value ignored.
4 Not used. Value ignored.
5 Not used. Value ignored.
6 Not used. Value ignored.
7 Not used. Value ignored.
0 8 Minimum System Voltage, DACMINSV 0 0 = Adds 0mV of system Voltage.
1 = Adds 256mV of system Voltage.
1 9 Minimum System Voltage, DACMINSV 1 0 = Adds 0mV of system Voltage.
1 = Adds 512mV of system Voltage.
2 10 Minimum System Voltage, DACMINSV 2 0 = Adds 0mV of system Voltage.
1 = Adds 1024mV of system Voltage.
3 11 Minimum System Voltage, DACMINSV 3 0 = Adds 0mV of system Voltage.
1 = Adds 2048mV of system Voltage.
4 12 Minimum System Voltage, DACMINSV 4 0 = Adds 0mV of system Voltage.
1 = Adds 4096mV of system Voltage.
5 13 Minimum System Voltage, DACMINSV 5 0 = Adds 0mV of system Voltage.
1 = Adds 8192mV of system Voltage.
6 14 Not used. 1 = invalid write.
7 15 Not used. 1 = invalid write.

Table 13. Default MaxChargeVoltage and System Voltage

NUMBER of CELLs MaxChargeVoltage() MinSystemVoltage()
Charge Enable Charge Disable
1S (CELL=GND) 4.192V 4.400V 3.584V
2S (CELL=FLOAT) 8.400V 9.008V 6.144V
3S/4S (CELL=High) 12.592V 13.500V 9.216V

Setting Input Current

Normally, input power source powers system and charges battery. With AC wall adapter output current can be regulated to save system cost.

To set the input current limit, write a 16-bit InputCurrent() command. When using a 10mΩ sense resistor, the bq2477x provides an input-current limit range of 128mA to 8.128A, with 64mA resolution. Upon POR, default input current limit is 3.2A (770) or 2.944A (773).

The ACP and ACN pins are used to sense R(AC) with default value of 10mΩ. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss.

Table 14. Input Current Register using 10mΩ sense resistor

I2C
0FH
SMBus
REG 0x3FH
BIT NAME DESCRIPTION
0 Not used. Value ignored.
1 Not used. Value ignored.
2 Not used. Value ignored.
3 Not used. Value ignored.
4 Not used. Value ignored.
5 Not used. Value ignored.
0 6 Input Current, DACIIN 0 0 = Adds 0mA of input current.
1 = Adds 64mA of input current.
1 7 Input Current, DACIIN 1 0 = Adds 0mA of input current.
1 = Adds 128mA of input current.
2 8 Input Current, DACIIN 2 0 = Adds 0mA of input current.
1 = Adds 256mA of input current.
3 9 Input Current, DACIIN 3 0 = Adds 0mA of input current.
1 = Adds 512mA of input current.
4 10 Input Current, DACIIN 4 0 = Adds 0mA of input current.
1 = Adds 1024mA of input current.
5 11 Input Current, DACIIN 5 0 = Adds 0mA of input current.
1 = Adds 2048mA of input current.
6 12 Input Current, DACIIN 6 0 = Adds 0mA of input current.
1 = Adds 4096mA of input current.
7 13 Not used. 1 = invalid write.
14 Not used. 1 = invalid write.
15 Not used. 1 = invalid write.