ZHCSG74B april   2017  – april 2023 AMC1301-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Sizing
        2. 8.2.2.2 Input Filter Design
        3. 8.2.2.3 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)

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Figure 6-5 Common-Mode Overvoltage Detection Level vs High-Side Supply Voltage
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VDD1 = 3.3 V
Figure 6-7 Input Offset Voltage Histogram
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Figure 6-9 Input Offset Voltage vs Supply Voltage
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VDD1 = 3.3 V
Figure 6-11 Input Offset Drift Histogram
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Figure 6-13 Common-Mode Rejection Ratio vs Input Frequency
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Figure 6-15 Input Bias Current vs Common-Mode Input Voltage
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Figure 6-17 Input Bias Current vs Temperature
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VDD1 = 3.3 V
Figure 6-19 Gain Error Histogram
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Figure 6-21 Gain Error vs Supply Voltage
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VDD1 = 3.3 V
Figure 6-23 Gain Error Drift Histogram
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Figure 6-25 Output Voltage vs Input Voltage
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Figure 6-27 Nonlinearity vs Supply Voltage
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Figure 6-29 Total Harmonic Distortion vs Supply Voltage
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Figure 6-31 Signal-to-Noise Ratio vs Input Voltage
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Figure 6-33 Signal-to-Noise Ratio vs Temperature
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vs VDD1
Figure 6-35 Power-Supply Rejection Ratio vs Ripple Frequency
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Figure 6-37 Output Rise and Fall Time vs Temperature
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Figure 6-39 VIN to VOUT Signal Delay vs Temperature
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Figure 6-41 Output Common-Mode Voltage vs Temperature
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Figure 6-43 Output Bandwidth vs Temperature
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Figure 6-45 Supply Current vs Temperature
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Figure 6-6 Common-Mode Overvoltage Detection Level vs Temperature
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VDD1 = 5 V
Figure 6-8 Input Offset Voltage Histogram
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Figure 6-10 Input Offset Voltage vs Temperature
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VDD1 = 5 V
Figure 6-12 Input Offset Drift Histogram
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Figure 6-14 Common-Mode Rejection Ratio vs Temperature
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Figure 6-16 Input Bias Current vs High-Side Supply Voltage
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Figure 6-18 Normalized Gain vs Input Frequency
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VDD1 = 5 V
Figure 6-20 Gain Error Histogram
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Figure 6-22 Gain Error vs Temperature
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VDD1 = 5 V
Figure 6-24 Gain Error Drift Histogram
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Figure 6-26 Nonlinearity vs Input Voltage
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Figure 6-28 Nonlinearity vs Temperature
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Figure 6-30 Total Harmonic Distortion vs Temperature
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Figure 6-32 Signal-to-Noise Ratio vs Supply Voltage
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Figure 6-34 Input-Referred Noise Density vs Frequency
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vs VDD2
Figure 6-36 Power-Supply Rejection Ratio vs Ripple Frequency
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Figure 6-38 VIN to VOUT Signal Delay vs Low-Side
Supply Voltage
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Figure 6-40 Output Common-Mode Voltage vs Low-Side
Supply Voltage
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Figure 6-42 Output Bandwidth vs Low-Side Supply Voltage
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Figure 6-44 Supply Current vs Supply Voltage