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PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
For more details about features and additional description information on the device (LP)DDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-36 and Figure 7-28 present switching characteristics for DDRSS.
NO. | PARAMETER | DDR TYPE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(DDR_CKP/DDR_CKN) | Cycle time, DDR_CKP and DDR_CKN | LPDDR4 | 1.25(1) | 20 | ns |
DDR4 | 1.25(1) | 1.6 | ns |
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.