ZHCSGC8A March   2014  – June 2017 AFE5401-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements: Output Interface
    8. 6.8  Timing Requirements: RESET
    9. 6.9  Timing Requirements: Serial Interface Operation
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Requirements: Across Output Serialization Modes
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Noise Amplifier (LNA)
      2. 8.3.2 Programmable Gain Amplifier (PGA)
      3. 8.3.3 Antialiasing Filter
      4. 8.3.4 Analog-to-Digital Converter (ADC)
      5. 8.3.5 Digital Gain
      6. 8.3.6 Input Clock Divider
      7. 8.3.7 Data Output Serialization
      8. 8.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 8.3.8.1 Main Channels
        2. 8.3.8.2 Auxiliary Channel
    4. 8.4 Device Functional Modes
      1. 8.4.1 Equalizer Mode
      2. 8.4.2 Data Output Mode
        1. 8.4.2.1 Header
        2. 8.4.2.2 Test Pattern Mode
      3. 8.4.3 Parity
      4. 8.4.4 Standby, Power-Down Mode
      5. 8.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 8.4.5.1 Decimate-by-2 Mode
        2. 8.4.5.2 Decimate-by-4 Mode
      6. 8.4.6 Diagnostic Mode
      7. 8.4.7 Signal Chain Probe
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Register Initialization
        1. 8.5.2.1 Register Write Mode
        2. 8.5.2.2 Register Read Mode
      3. 8.5.3 CMOS Output Interface
        1. 8.5.3.1 Synchronization and Triggering
    6. 8.6 Register Maps
      1. 8.6.1 Functional Register Map
      2. 8.6.2 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Parameter Measurement Information

7.1 Timing Requirements: Across Output Serialization Modes

Table 1 and Table 2 provide details for the 4x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 3 and Table 4 provide details for the 3x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 5 provides the details for the 2x and 1x serialization timing requirements for DRVDD = 1.8 V to 3.3 V.

Table 1. Timing Requirements: 4x Serialization (DRVDD = 3.3 V)

INPUT CLOCK FREQUENCY (MHz) OUTPUT CLOCK (DCLK) FREQUENCY (MHz) TEST CONDITIONS SETUP TIME (ns)
tSU 		HOLD TIME (ns)
tHO 		tOUT (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
12.5 50 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 9.1 7.9 6.7 9.5
15 60 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 7.1 6.1 6.7 9.5
20 80 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 5.3 4.1 6.7 9.5
25 100 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 4.1 2.8 6.7 9.5
25 100 CLOAD = 15 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 6		 3.5 2.6 6.4 9.0

Table 2. Timing Requirements: 4x Serialization (DRVDD = 1.8 V)

INPUT CLOCK FREQUENCY (MHz) OUTPUT CLOCK (DCLK) FREQUENCY (MHz) TEST CONDITIONS SETUP TIME (ns)
tSU 		HOLD TIME (ns)
tHO 		tOUT (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
12.5 50 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 9.2 7.9 5.6 10.6
15 60 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 7.2 6.1 5.6 10.6
20 80 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 5.3 3.9 5.6 10.6
25 100 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 3.7 2.7 5.6 10.6
25 100 CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14		 2.6 2.7 5.3 10.0

Table 3. Timing Requirements: 3x Serialization (DRVDD = 3.3 V)

INPUT CLOCK FREQUENCY (MHz) OUTPUT CLOCK (DCLK) FREQUENCY (MHz) TEST CONDITIONS SETUP TIME (ns)
tSU 		HOLD TIME (ns)
tHO 		tOUT (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
12.5 37.5 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 12.4 11.8 20.1 23.2
15 45 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 9.9 9.1 17.4 20.4
20 60 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 7.2 6.3 15.1 18.0
25 75 CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		 5.7 4.1 13.4 16.0
25 75 CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 6		 5.1 3.8 12.8 15.3

Table 4. Timing Requirements: 3x Serialization (DRVDD = 1.8 V)

INPUT CLOCK FREQUENCY (MHz) OUTPUT CLOCK (DCLK) FREQUENCY (MHz) TEST CONDITIONS SETUP TIME (ns)
tSU 		HOLD TIME (ns)
tHO 		tOUT (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
12.5 37.5 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 12.5 11.9 19.2 23.6
15 45 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 10.0 9.3 16.6 20.1
20 60 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 7.3 6.4 14.0 18.4
25 75 CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		 5.7 4.7 12.4 16.7
25 75 CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14		 4.7 4 12.1 16.4

Table 5. Timing Requirements: 2x and 1x Serialization (DRVDD = 1.8 V to 3.3 V)

INPUT CLOCK FREQUENCY (MHz) OUTPUT CLOCK (DCLK) FREQUENCY (MHz) TEST CONDITIONS SETUP TIME (ns)
tSU 		HOLD TIME (ns)
tHO 		tOUT (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
25 50 2x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.		 7.3 8.0 5.5 10.5
25 25 1x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.		 18.5 17.5 25.2 30.1