ZHCSDV4C 数据表 | 德州仪器 TI.com.cn

ZHCSDV4C June 2015 – May 2016 AFE4404

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YZP|15

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	RX_SUP to GND	–0.3	4	V
	IO_SUP to GND	–0.3	4
	RX_SUP-IO_SUP	–0.3
	TX_SUP to GND	–0.3	6
Voltage applied to analog inputs		Max [–0.3, (GND – 0.3)]	Min [4, (RX_SUP + 0.3)]	V
Voltage applied to digital inputs		Max [–0.3, (GND – 0.3)]	Min [4, (IO_SUP + 0.3)]	V
Maximum duty cycle (cumulative): sum of all LED phase durations as a function of the total period	50-mA LED current mode (ILED_2X = 0)		10%
	100-mA LED current mode (ILED_2X = 1)		3%
Storage temperature, T_stg		–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
RX_SUP	Receiver supply		2	3.6	V
IO_SUP	Input/output supply		1.7	Min (3.6, RX_SUP)	V
TX_SUP	Transmitter supply	50-mA LED current mode (ILED_2X = 0)	3.0 or (0.5 + V_LED)⁽¹⁾, whichever is greater	5.25	V
TX_SUP	Transmitter supply	100-mA LED current mode (ILED_2X = 1)	3.0 or (1.0 + V_LED)⁽¹⁾, whichever is greater	5.25	V
	Digital inputs		0	IO_SUP	V
	Analog inputs		0	RX_SUP	V
	Operating temperature range		–20	70	°C

(1) V_LED refers to the maximum voltage drop across the external LED (at maximum LED current). This value is usually governed by the forward drop voltage (V_FB) of the LED.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		AFE4404	UNIT
		YZP (DSBGA)
		15 BALLS
R_θJA	Junction-to-ambient thermal resistance	67.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.5	°C/W
R_θJB	Junction-to-board thermal resistance	12.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	12.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Minimum and maximum specifications are at T_A = –20°C to 70°C, typical specifications are at 25°C. TX_SUP = 4 V, RX_SUP = IO_SUP = 3 V, 100-Hz PRF, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), detector C_IN = 50 pF, and CLKDIV_PRF set to 1, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
PULSE REPETITION FREQUENCY
PRF⁽¹⁾	Pulse repetition frequency		10⁽⁷⁾		1000	SPS
RECEIVER
	Offset cancellation DAC current range			–7 to 7		µA
	Offset cancellation DAC current step			0.47		µA
	TIA gain setting			10k to 2M		Ω
	C_f setting			2.5 to 25		pF
	Switched RC filter bandwidth			2.5⁽²⁾		kHz
	ADC averages		1		16
	Detector capacitance	Differential capacitance between INP, INN	10		200	pF
TRANSMITTER
	LED current range	ILED_2X = 0		0 to 50		mA
	LED current range	ILED_2X = 1		0 to 100		mA
	LED current resolution			6		Bits
CLOCKING (Internal Oscillator)
	Frequency			4		MHz
	Accuracy	Room temperature		±1%
	Frequency drift with temperature	Full temperature range		±0.5%
	Jitter (RMS)			100		ps
	Output clock high level			IO_SUP		V
	Output clock low level			0		V
	Output clock rise and fall times	10% to 90%, 15-pF load capacitance on CLK pin		< 30		ns
CLOCKING (External Clock)
	Frequency range⁽³⁾		4		60	MHz
	Input clock high level			IO_SUP		V
	Input clock low level			0		V
	Input capacitance of CLK pin	Capacitance to ground		< 4		pF
I²C INTERFACE
	Maximum clock speed			400		kHz
	I²C slave address			58		Hex
PERFORMANCE
	Receiver SNR	SNR over a 20-Hz bandwidth for a 500-kΩ gain setting, 50% FS output, 2% LED and sampling pulse duration, ADC averages set to 16		100		dBFS⁽⁶⁾
	Transmitter SNR	SNR over a 20-Hz bandwidth for a 50-mA LED current setting		100		dBFS⁽⁶⁾
CURRENT CONSUMPTION
	RX_SUP current	Normal operation, external clock mode		620		µA
		Normal operation, internal oscillator mode		670
		In dynamic power-down mode⁽⁸⁾		300
		Hardware power-down (PWDN) mode⁽⁹⁾		3
		Software power-down (PDNAFE) mode⁽⁹⁾		35
	IO_SUP current	Normal operation, external clock mode		20		µA
		Normal operation, internal oscillator mode		5
		In dynamic power-down mode⁽⁸⁾		20
		Hardware power-down (PWDN) mode⁽⁹⁾		3
		Software power-down (PDNAFE) mode⁽⁹⁾		5
	TX_SUP current	Normal operation, external clock mode⁽¹⁰⁾		25		µA
		Normal operation, internal oscillator mode⁽¹⁰⁾		25
		In dynamic power-down mode⁽⁸⁾⁽¹⁰⁾		5
		Hardware power-down (PWDN) mode⁽⁹⁾⁽¹⁰⁾		2
		Software power-down (PDNAFE) mode⁽⁹⁾⁽¹⁰⁾		2
TRANSIENT RECOVERY
t_ACTIVE	Recovery from PWDN mode	Time for signal chain to be functional⁽⁴⁾		10		ms
t_CHANNEL	Recovery from any event causing a change in signal characteristics	PRF = 100 Hz, sampling duty cycle (each phase) of 2%⁽⁵⁾		200		ms
DIGITAL INPUTS
V_IH	High-level input voltage		0.9 × IO_SUP	IO_SUP		V
V_IL	Low-level input voltage			0	0.1 × IO_SUP	V
DIGITAL OUTPUTS
V_OH	High-level output voltage			IO_SUP		V
V_OL	Low-level output voltage			0		V

(1) PRF refers to the rate at which samples from each of the four phases are output from the AFE.

(2) The effective bandwidth of the switched RC filter scales as a function of the sampling duty cycle. For example, at 2% sampling width duty cycle, the effective bandwidth of the switched RC filter is approximately 50 Hz.

(3) With appropriate setting of the clock divider ratio (CLKDIV_EXTMODE).

(4) For full performance to be restored, a longer time as governed by t_CHANNEL can be applicable.

(5) t_CHANNELscales inversely with the sampling duty cycle.

(6) dBFS refers to a full-scale voltage of 2 V.

(7) To extend the lower range of PRF down to 10 Hz, program the CLKDIV_PRF setting.

(8) In dynamic power-down mode for 90% and active mode for 10% of the period.

(9) External clock mode with the external clock switched off.

(10) LED currents set to 0 mA.

7.6 Timing Requirements

		TYP	UNIT
t_{I2C_RISE}	I²C data rise time with a 10-kΩ pullup resistor with a 20-pF load from I²C data to GND	1200	ns
t_{I2C_FALL}	I²C data fall time (when the data line is pulled down by the AFE) with a 20-pF load from I²C data to GND	28	ns
t_{ADC_RDY_RISE}	ADC_RDY rise time (10% to 90%) with a 15-pF capacitive load to ground	21	ns
t_{ADC_RDY_FALL}	ADC_RDY fall time (90% to 10%) with a 15-pF capacitive load to ground	21	ns

7.7 Typical Characteristics

At 25°C, TX_SUP = 4 V, RX_SUP = IO_SUP = 3.3 V, 100-Hz PRF, 25% duty cycle, R_f = 500 kΩ, C_f is adjusted to keep the TIA time constant at 1/10th of the sampling duration, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), CLKDIV_PRF = 1, detector C_IN = 50 pF, ADC averaging = max allowed, SNR (dBFS) = noise referred to full-scale range of 2 V, noise integrated from 1 Hz to Nyquist (= PRF / 2), and values assigned to CLKDIV_EXTMODE and CLK_DIV_PRF parameters correspond to division ratios controlled by these modes, unless otherwise specified.

Figure 1. Receiver Current vs External Clock Frequency

Duty cycle (x-axis) refers to the sampling duration expressed as a percentage of the pulse repetition period.

Figure 3. Input-Referred Noise Current in 20-Hz Bandwidth vs Duty Cycle for Different Output Levels
(As a Percentage of Full-Scale)

Figure 5. Receiver Input-Referred Noise Current in 20-Hz BW vs Duty Cycle (Different TIA Gain Settings)

Figure 7. Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)

Figure 9. Input-Referred Noise Current in Nyquist Bandwidth vs Duty Cycle (Different Decimation Factor)

PRF = 2000 Hz

Figure 11. Response of the Switched-RC Filter
at the AFE Output

Figure 13. Filter Response for Multiple PRFs at
5% Duty Cycle

Figure 15. LED Current vs Transmitter Headroom Voltage

Figure 17. Transmitter DAC Current Step Error in
100-mA Mode

Duty cycle = 1%

Figure 19. PSRR vs Tone Frequency at RX_SUP

Figure 21. Receiver SNR in a 20-Hz Bandwidth vs
Duty Cycle Across Different Temperatures

Active window = 500 µs, LED pulse = 100 µs,
all four DYNAMIC bits set to 1

Figure 2. Receiver Current vs PRF in
Dynamic Power-Down Mode

Duty cycle (x-axis) refers to the sampling duration expressed as a percentage of the pulse repetition period.

Figure 4. Signal-to-Noise Ratio in 20-Hz Bandwidth vs Duty Cycle for Different Output Levels
(As a Percentage of Full-Scale)

Figure 6. Receiver SNR in 20-Hz BW vs Duty Cycle
(Different TIA Gain Settings)

Figure 8. Receiver Signal-to-Noise Ratio over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)

Figure 10. Receiver Input-Referred Noise in 20-Hz Bandwidth vs Duty Cycle
(Different Offset Cancellation DAC Currents)

Figure 12. Filter Response for Multiple PRFs at
1% Duty Cycle

Figure 14. Transmitter Current Linearity

Figure 16. Transmitter DAC Current Step Error in
50-mA Mode

Duty cycle = 1%

Figure 18. PSRR vs Tone Frequency at TX_SUP

PRF = 200 Hz, NUMAV = 0

Figure 20. Rejection of a 50-Hz Differential Tone Across Spacing Between LED and Ambient Phases

Figure 22. Internal Oscillator Frequency vs
Temperature on a Typical Unit