SBASAQ6 April 2024 ADS9813
ADVANCE INFORMATION
Operate the ADS9813 with a differential or a single-ended clock input where the single-ended clock consumes less power consumption. Make sure the sampling clock is a free-running continuous clock. After a free-running sampling clock is applied, the ADC generates valid output data, the data clock, and the frame clock tPU_SMPL_CLK. These parameters are specified in the Switching Characteristics section. The ADC output data, data clock, and frame clock are invalid when the sampling clock is stopped.
Figure 6-4 and Figure 6-5 show that the sampling clock is either differential or single-ended, respectively.