ZHCSR17 january   2023 ADS9218

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: ADS9218
    10. 6.10 Typical Characteristics: ADS9217
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference
        1. 7.3.4.1 Internal Reference Voltage
        2. 7.3.4.2 External Reference Voltage
      5. 7.3.5 Data Interface
        1. 7.3.5.1 Data Frame Width
        2. 7.3.5.2 Test Patterns for Data Interface
          1. 7.3.5.2.1 User-Defined Test Pattern
          2. 7.3.5.2.2 User-Defined Alternating Test Pattern
          3. 7.3.5.2.3 Ramp Test Pattern
      6. 7.3.6 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power-Down Options
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
    6. 7.6 Register Map
      1. 7.6.1 Register Bank 0
      2. 7.6.2 Register Bank 1
      3. 7.6.3 Register Bank 2
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.3 Register Bank 2

Figure 7-62 Register Bank 2 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1Ch RESERVED TMP_REG_L1C_1 RESERVED
22h RESERVED TMP_REG_L22_2 TMP_REG_L22_1 RESERVED
33h RESERVED TMP_REG_L33_1 RESERVED
52h RESERVED TMP_REG_L52_2 TMP_REG_L52_1
53h RESERVED TMP_REG_L53_1
54h TMP_REG_L54_5 TMP_REG_L54_4 TMP_REG_L54_3 TMP_REG_L54_2 TMP_REG_L54_1 RESERVED
56h RESERVED TMP_REG_L56_3 TMP_REG_L56_2 TMP_REG_L56_1 RESERVED
57h RESERVED TMP_REG_L57_1 RESERVED
60h TMP_REG_L60_1 RESERVED

7.6.3.1 Register 1Ch (offset = 1Ch) [reset = 0h]

Figure 7-63 Register 1Ch
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L1C_1
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-64 Register 1C Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED R/W 0h Reserved. Do not change from default reset value.
8-8 TMP_REG_L1C_1 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
7-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.2 Register 22h (offset = 22h) [reset = 0h]

Figure 7-65 Register 22h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L22_2 TMP_REG_L22_1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-66 Register 22 Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h Reserved. Do not change from default reset value.
12-12 TMP_REG_L22_2 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
11-11 TMP_REG_L22_1 R/W 0h Temporary Register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
10-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.3 Register 33h (offset = 33h) [reset = 0h]

Figure 7-67 Register 33h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L33_1 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-68 Register 33 Field Descriptions
Bit Field Type Reset Description
15-11 RESERVED R/W 0h Reserved. Do not change from default reset value.
10-10 TMP_REG_L33_1 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
9-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.4 Register 52h (offset = 52h) [reset = 0h]

Figure 7-69 Register 52h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED TMP_REG_L52_2 TMP_REG_L52_1
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-70 Register 52 Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R/W 0h Reserved. Do not change from default reset value.
1-1 TMP_REG_L52_2 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
0-0 TMP_REG_L52_1 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation

7.6.3.5 Register 53h (offset = 53h) [reset = 0h]

Figure 7-71 Register 53h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h TMP_REG_L53_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-72 Register 53 Field Descriptions
Bit Field Type Reset Description
15-1 RESERVED R/W 0h Reserved. Do not change from default reset value.
0-0 TMP_REG_L53_1 R/W 0h Temporary register.

0 : Normal device operation
1 : Not recommended

7.6.3.6 Register 54h (offset = 54h) [reset = 0h]

Figure 7-73 Register 54h
15 14 13 12 11 10 9 8
TMP_REG_L54_5 TMP_REG_L54_4 TMP_REG_L54_3 TMP_REG_L54_2 TMP_REG_L54_1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-74 Register 54 Field Descriptions
Bit Field Type Reset Description
15-15 TMP_REG_L54_5 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
14-14 TMP_REG_L54_4 R/W 0h Temporary register. Write 0b for normal device operation.
0 : Normal device operation
1 : Not recommended
13-13 TMP_REG_L54_3 R/W 0h Temporary register. Write 0b for normal device operation.
0 : Normal device operation
1 : Not recommended
12-12 TMP_REG_L54_2 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
11-11 TMP_REG_L54_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
10-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.7 Register 56h (offset = 56h) [reset = 0h]

Figure 7-75 Register 56h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L56_3 TMP_REG_L56_2 TMP_REG_L56_1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-76 Register 56 Field Descriptions
Bit Field Type Reset Description
15-15 RESERVED R/W 0h Reserved. Do not change from default reset value.
14-14 TMP_REG_L56_3 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
13-13 TMP_REG_L56_2 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
12-12 TMP_REG_L56_1 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
11-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.8 Register 57h (offset = 57h) [reset = 0h]

Figure 7-77 Register 57h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L57_1 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-78 Register 57 Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h Reserved. Do not change from default reset value.
11-11 TMP_REG_L57_1 R/W 0h Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
10-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.3.9 Register 60h (offset = 60h) [reset = 0h]

Figure 7-79 Register 60h
15 14 13 12 11 10 9 8
TMP_REG_L60_1 RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-80 Register 60 Field Descriptions
Bit Field Type Reset Description
15-15 TMP_REG_L60_1 R/W 0h Temporary register. Write 1b for normal device operation.

0 : Not recommended
1 : Normal device operation
14-0 RESERVED R/W 0h Reserved. Do not change from default reset value.