ZHCSIK6C November 2017 – November 2019 ADS8166 , ADS8167 , ADS8168
PRODUCTION DATA.
This register selects the margining to be added to or subtracted from the REFFby2 buffer output; see the REFby2 Buffer section.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | REFby2_OFST[2:0] | 0 | 0 | 0 | EN_REFby2_MARG | ||
R-0b | R/W-000b | R-0b | R-0b | R-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R | 0b | Reserved bit. Do not write. Reads return 0b. |
6-4 | REFBY2_OFST[2:0] | R/W | 000b | These bits select the REFby2 offset value as per Table 26. |
3-1 | 0 | R | 000b | Reserved bits. Do not write. Reads return 000b. |
0 | EN_REFby2_MARG | R/W | 0b | This bit enables the REFby2 buffer margining feature.
0b = Margining is disabled 1b = Margining is enabled |
REFby2_OFST[2:0] | VREFby2(1)
(VREF = 4.096 V) |
VREFby2(1)
(VREF = 5 V) |
---|---|---|
EN_REFby2_MARG = 0b | 2.04800 V | 2.50000 V |
000b | 2.12611 V | 2.59155 V |
001b | 2.13008 V | 2.59640 V |
010b | 2.13406 V | 2.60124 V |
011b | 2.13804 V | 2.60610 V |
100b | 2.14203 V | 2.61096 V |
101b | 2.14602 V | 2.61581 V |
110b | 2.14999 V | 2.62065 V |
111b | 2.15397 V | 2.62550 V |