ZHCSEJ4C May   2015  – January 2017 ADS54J69

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame Assembly with Decimation
          1. 8.4.2.4.1 JESD Transmitter Interface
          2. 8.4.2.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Info
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1 General Registers
          1. 8.5.3.1.1 Register 0h (address = 0h)
          2. 8.5.3.1.2 Register 3h (address = 3h)
          3. 8.5.3.1.3 Register 4h (address = 4h)
          4. 8.5.3.1.4 Register 5h (address = 5h)
          5. 8.5.3.1.5 Register 11h (address = 11h)
        2. 8.5.3.2 Master Page (080h) Registers
          1. 8.5.3.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.3.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.3.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.3.2.6  Register 39h (address = 39h), Master Page (080h)
          7. 8.5.3.2.7  Register 3Ah (address = 3Ah), Master Page (080h)
          8. 8.5.3.2.8  Register 4Fh (address = 4Fh), Master Page (080h)
          9. 8.5.3.2.9  Register 53h (address = 53h), Master Page (080h)
          10. 8.5.3.2.10 Register 54h (address = 54h), Master Page (080h)
          11. 8.5.3.2.11 Register 55h (address = 55h), Master Page (080h)
          12. 8.5.3.2.12 Register 56h (address = 56h), Master Page (080h)
          13. 8.5.3.2.13 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.3.3 ADC Page (0Fh) Registers
          1. 8.5.3.3.1 Registers 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.3.4 Main Digital Page (6800h) Registers
          1. 8.5.3.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.3.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.3.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.3.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.3.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.3.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.3.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.3.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.3.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.3.5 JESD Digital Page (6900h) Registers
          1. 8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.3.5.8 Register 31h (address = 31h), JESD Digital Page (6900h)
          9. 8.5.3.5.9 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.3.6 JESD Analog Page (6A00h) Register
          1. 8.5.3.6.1 Registers 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.3.6.3 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          4. 8.5.3.6.4 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range AVDD3V –0.3 3.6 V
AVDD –0.3 2.1
DVDD –0.3 2.1
IOVDD –0.2 1.4
Voltage between AGND and DGND –0.3 0.3 V
Voltage applied to input pins INAP, INBP, INAM, INBM –0.3 3 V
CLKINP, CLKINM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 AVDD + 0.3
SCLK, SEN, SDIN, RESET, SYNC, PDN –0.2 2.1
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(2)(3)
MIN NOM MAX UNIT
Supply voltage range AVDD3V 2.85 3.0 3.6 V
AVDD 1.8 1.9 2.0
DVDD 1.7 1.9 2.0
IOVDD 1.1 1.15 1.2
Analog inputs Differential input voltage range 1.9 VPP
Input common-mode voltage 2.0 V
Maximum analog input frequency for 1.9-VPP input amplitude(4)(5) 400 MHz
Clock inputs Input clock frequency, device clock frequency 500 1000 MHz
Input clock amplitude differential
(VCLKP – VCLKM)		 Sine wave, ac-coupled 0.75 1.5 VPP
LVPECL, ac-coupled 0.8 1.6
LVDS, ac-coupled 0.7
Input device clock duty cycle 45% 50% 55%
Temperature Operating free-air, TA –40 85 ºC
Operating junction, TJ 105(1) 125
(1) Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.
(2) SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.
(3) After power-up, always use a hardware reset to reset the device for the first time; see Table 60 for details.
(4) Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.
(5) At high frequencies, the maximum supported input amplitude reduces; see Figure 51 for details.

7.4 Thermal Information

THERMAL METRIC(1) ADS54J69 UNIT
RMP (VQFNP)
72 PINS
RθJA Junction-to-ambient thermal resistance 22.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 5.1 °C/W
RθJB Junction-to-board thermal resistance 2.4 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 2.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
Device clock frequency 1000 MSPS
Output sample rate 500 MSPS
Resolution 16 Bits
POWER SUPPLIES
AVDD3V 3.0-V analog supply 2.85 3.0 3.6 V
AVDD 1.9-V analog supply 1.8 1.9 2.0 V
DVDD 1.9-V digital supply 1.7 1.9 2.0 V
IOVDD 1.15-V SERDES supply 1.1 1.15 1.2 V
IAVDD3V 3.0-V analog supply current VIN = full-scale on both channels 293 360 mA
IAVDD 1.9-V analog supply current VIN = full-scale on both channels 354 510 mA
IDVDD 1.9-V digital supply current Four-lane output mode
(default after reset)		 188 260 mA
IIOVDD 1.15-V SERDES supply current 512 920 mA
Pdis Total power dissipation 2.66 3.1 W
IDVDD 1.9-V digital supply current Two-lane output mode 195 mA
IIOVDD 1.15-V SERDES supply current 559 mA
Pdis Total power dissipation 2.73 W
Global power-down power dissipation Using the GLOBAL PDN register bit in the master page 204 315 mW

7.6 AC Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR Signal-to-noise ratio fIN = 10 MHz, AIN = –1 dBFS 74.2 dBFS
fIN = 140 MHz, AIN = –1 dBFS 73.4
fIN = 170 MHz, AIN = –1 dBFS 71.3 73
fIN = 210 MHz, AIN = –1 dBFS 72.7
fIN = 310 MHz, AIN = –1 dBFS 71.7
fIN = 370 MHz, AIN = –1 dBFS 70.3
fIN = 470 MHz, AIN = –3 dBFS 70.5
NSD Noise spectral density fIN = 10 MHz, AIN = –1 dBFS 158.2 dBFS/Hz
fIN = 140 MHz, AIN = –1 dBFS 157.4
fIN = 170 MHz, AIN = –1 dBFS 155.3 157.0
fIN = 210 MHz, AIN = –1 dBFS 156.7
fIN = 310 MHz, AIN = –1 dBFS 155.7
fIN = 370 MHz, AIN = –1 dBFS 154.3
fIN = 470 MHz, AIN = –3 dBFS 154.5
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz, AIN = –1 dBFS 73.8 dBFS
fIN = 140 MHz, AIN = –1 dBFS 73.3
fIN = 170 MHz, AIN = –1 dBFS 69.8 72.9
fIN = 210 MHz, AIN = –1 dBFS 72.5
fIN = 310 MHz, AIN = –1 dBFS 71.2
fIN = 370 MHz, AIN = –1 dBFS 70.2
fIN = 470 MHz, AIN = –3 dBFS 69.4
SFDR Spurious free dynamic range (excluding IL spurs) fIN = 10 MHz, AIN = –1 dBFS 86 dBc
fIN = 140 MHz, AIN = –1 dBFS 95
fIN = 170 MHz, AIN = –1 dBFS 79 94
fIN = 210 MHz, AIN = –1 dBFS 89
fIN = 310 MHz, AIN = –1 dBFS 81
fIN = 370 MHz, AIN = –1 dBFS 87
fIN = 470 MHz, AIN = –3 dBFS 73
HD2 Second-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 86 dBc
fIN = 140 MHz, AIN = –1 dBFS 104
fIN = 170 MHz, AIN = –1 dBFS 85 102
fIN = 210 MHz, AIN = –1 dBFS 95
fIN = 310 MHz, AIN = –1 dBFS 81
fIN = 370 MHz, AIN = –1 dBFS 87
fIN = 470 MHz, AIN = –3 dBFS 96
HD3 Third-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 89 dBc
fIN = 140 MHz, AIN = –1 dBFS 103
fIN = 170 MHz, AIN = –1 dBFS 86 101
fIN = 210 MHz, AIN = –1 dBFS 100
fIN = 310 MHz, AIN = –1 dBFS 98
fIN = 370 MHz, AIN = –1 dBFS 95
fIN = 470 MHz, AIN = –3 dBFS 73
Non
HD2, HD3		 Spurious-free dynamic range
(excluding HD2, HD3, and IL spur)		 fIN = 10 MHz, AIN = –1 dBFS 98 dBc
fIN = 140 MHz, AIN = –1 dBFS 95
fIN = 170 MHz, AIN = –1 dBFS 84 94
fIN = 210 MHz, AIN = –1 dBFS 89
fIN = 310 MHz, AIN = –1 dBFS 92
fIN = 370 MHz, AIN = –1 dBFS 97
fIN = 470 MHz, AIN = –3 dBFS 92
ENOB Effective number of bits fIN = 10 MHz, AIN = –1 dBFS 12 Bits
fIN = 140 MHz, AIN = –1 dBFS 11.9
fIN = 170 MHz, AIN = –1 dBFS 11.3 11.9
fIN = 210 MHz, AIN = –1 dBFS 11.8
fIN = 310 MHz, AIN = –1 dBFS 11.5
fIN = 370 MHz, AIN = –1 dBFS 11.4
fIN = 470 MHz, AIN = –3 dBFS 11.2
THD Total harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 84 dBc
fIN = 140 MHz, AIN = –1 dBFS 95
fIN = 170 MHz, AIN = –1 dBFS 79 89
fIN = 210 MHz, AIN = –1 dBFS 85
fIN = 310 MHz, AIN = –1 dBFS 80
fIN = 370 MHz, AIN = –1 dBFS 85
fIN = 470 MHz, AIN = –3 dBFS 72
SFDR_IL Interleaving spur fIN = 10 MHz, AIN = –1 dBFS 90 dBc
fIN = 140 MHz, AIN = –1 dBFS 90
fIN = 170 MHz, AIN = –1 dBFS 75 87
fIN = 210 MHz, AIN = –1 dBFS 85
fIN = 310 MHz, AIN = –1 dBFS 85
fIN = 370 MHz, AIN = –1 dBFS 86
fIN = 470 MHz, AIN = –3 dBFS 82
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 185 MHz, fIN2 = 190 MHz,
AIN = –7 dBFS 		86 dBFS
fIN1 = 365 MHz, fIN2 = 370 MHz,
AIN = –7 dBFS 		79
fIN1 = 465 MHz, fIN2 = 470 MHz,
AIN = –10 dBFS 		78

7.7 Digital Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)(1)
VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.8 V
VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDIN, PDN, SYNC 50
IIL Low-level input current SEN 50 µA
RESET, SCLK, SDIN, PDN, SYNC 0
DIGITAL INPUTS (SYSREFP, SYSREFM)
VD Differential input voltage 0.35 0.45 1.4 V
V(CM_DIG) Common-mode voltage for SYSREF(4) 1.3 V
DIGITAL OUTPUTS (SDOUT, PDN(3))
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOD Output differential voltage With default swing setting 700 mVPP
VOC Output common-mode voltage 450 mV
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground		 2 pF
(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ (typical) pullup resistor to IOVDD.
(2) 100-Ω differential termination.
(3) When functioning as an OVR pin for channel B.
(4) The SYSREFP and SYSREFM pins are internally biased to the 1.3-V common-mode voltage through a 5-kΩ resistor.

7.8 Timing Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted)
MIN TYP MAX UNITS
SAMPLE TIMING
Aperture delay 0.75 1.6 ns
Aperture delay matching between two channels on the same device ±70 ps
Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps
Aperture jitter Actual jitter of sampling clock buffer 145 fS rms
Effective jitter after decimation filtering 102
WAKE-UP TIMING
Wake-up time to valid data after coming out of global power-down 150 µs
LATENCY
Data latency(1): ADC sample to digital output 134(2) Input clock cycles
OVR latency: ADC sample to OVR bit 62 Input clock cycles
FOVR latency: ADC sample to FOVR signal on pin 18 + 4 ns Input clock cycles
tPD Propagation delay: logic gates and output buffers delay (does not change with fS) 4 ns
SYSREF TIMING
tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge 300 900 ps
tH_SYSREF Hold time for SYSREF, referenced to the input clock falling edge 100 ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval 100 400 ps
Serial output data rate 2.5 10 Gbps
Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk
tR, tF Data rise time, data fall time: rise and fall times are measured from 20% to 80%,
differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps		 35 ps
(1) Overall latency = data latency + decimation filter delay + tPDI.
(2) Decimation filter latency is not included in this specification.
ADS54J69 digital_characterstics_sbas706.gif Figure 1. SYSREF Timing
ADS54J69 timing_characterstics_sbas713.gif Figure 2. Sample Timing Requirements

7.9 Typical Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted)
ADS54J69 D001_SBAS713.gif
SNR = 74.2 dBFS; SFDR = 86 dBc; SINAD = 73.8 dBFS;
THD = 83 dBc; HD2 = 86 dBc; HD3 = 89 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 98 dBc
Figure 3. FFT for 10-MHz Input Signal
ADS54J69 D003_SBAS713.gif
SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS;
THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc
Figure 5. FFT for 170-MHz Input Signal
ADS54J69 D005_SBAS713.gif
SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS;
THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc;
IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc
Figure 7. FFT for 310-MHz Input Signal
ADS54J69 D007_SBAS713.gif
SNR = 70.6 dBFS; SFDR = 86 dBc; SINAD = 70.55 dBFS;
THD = 85 dBc; tone at –3 dBFS; HD2 = 102 dBc; HD3 = 86 dBc;
IL spur = 97 dBc; non HD2, HD3 spur = 96 dBc
Figure 9. FFT for 470-MHz Input Signal
ADS54J69 D009_SBAS713.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS,
IMD = 101 dBFS
Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)
ADS54J69 D011_SBAS713.gif
fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –36 dBFS,
IMD3 = 102 dBFS
Figure 13. FFT for Two-Tone Input Signal (–36 dBFS)
ADS54J69 D013_SBAS713.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS,
IMD3 = 104 dBFS
Figure 15. FFT for Two-Tone Input Signal (–36 dBFS)
ADS54J69 D015_SBAS713.gif
fIN1 = 300 MHz, fIN2 = 310 MHz
Figure 17. Intermodulation Distortion vs
Input Amplitude (365 MHz and 370 MHz)
ADS54J69 D017_SBAS713.gif
Figure 19. Spurious-Free Dynamic Range vs
Input Frequency
ADS54J69 D019_SBAS713.gif
Figure 21. Signal-to-Noise Ratio vs Input Frequency
ADS54J69 D021_SBAS713.gif
fIN = 185 MHz
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADS54J69 D023_SBAS713.gif
fIN = 300 MHz
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADS54J69 D025_SBAS713.gif
fIN = 185 MHz
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADS54J69 D027_SBAS713.gif
fIN = 300 MHz
Figure 29. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADS54J69 D029_SBAS713.gif
fIN = 185 MHz
Figure 31. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
ADS54J69 D031_SBAS713.gif
fIN = 300 MHz
Figure 33. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
ADS54J69 D033_SBAS713.gif
Figure 35. Spurious-Free Dynamic Range vs
Gain and Input Frequency
ADS54J69 D035_SBAS713.gif
Figure 37. Third-Order Harmonic Distortion vs
Gain and Input Frequency
ADS54J69 D037_SBAS713.gif
fIN = 185 MHz
Figure 39. Performance vs Amplitude
ADS54J69 D039_SBAS713.gif
fIN = 185 MHz
Figure 41. IL Spur vs Amplitude
ADS54J69 D041_SBAS713.gif
fIN = 185 MHz
Figure 43. Performance vs Differential Clock Amplitude
ADS54J69 D043_SBAS713.gif
fIN = 185 MHz
Figure 45. Performance vs Input Clock Duty Cycle
ADS54J69 D045_SBAS713.gif
AIN = –1 dBFS, SFDR = 84 dBc, SINAD = 70 dBFS,
fPSRR = 5 MHz, APSRR = 50 mVPP, fIN = 185 MHz,
amplitude: fIN – fPSRR = 85 dBc, fIN + fPSRR = 84 dBc
Figure 47. Power-Supply Rejection Ratio FFT for
AVDD Supply
ADS54J69 D047_SBAS713.gif
AIN = –1 dBFS, SFDR = 78 dBc, SINAD = 71 dBFS,
fCMRR = 5 MHz, ACMRR = 50 mVPP, fIN = 185 MHz,
amplitude: fIN – fCMRR = 79 dBc, fIN + fCMRR = 80 dBc
Figure 49. Common-Mode Rejection Ratio FFT
ADS54J69 D049_SBAS713.gif
Figure 51. Maximum-Supported Amplitude vs
Input Frequency
ADS54J69 D051_SBAS713.gif
Figure 53. Signal-to-Noise Ratio vs
Input Frequency (Output Sample Rate = 300 MSPS)
ADS54J69 D053_SBAS713.gif
Figure 55. Signal-to-Noise Ratio vs Input Frequency
(Output Sample Rate = 350 MSPS)
ADS54J69 D055_SBAS713.gif
Figure 57. Signal-to-Noise Ratio vs Input Frequency
(Output Sample Rate = 400 MSPS)
ADS54J69 D002_SBAS713.gif
SNR = 73.3 dBFS; SFDR = 94 dBc; SINAD = 73.25 dBFS;
THD = 93 dBc; HD2 = 104 dBc; HD3 = 111 dBc;
IL spur = 95 dBc; non HD2, HD3 spur = 94 dBc
Figure 4. FFT for 140-MHz Input Signal
ADS54J69 D004_SBAS713.gif
SNR = 72.8 dBFS; SFDR = 89 dBc; SINAD = 72.63 dBFS;
THD = 86 dBc; HD2 = 97 dBc; HD3 = 99 dBc;
IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc
Figure 6. FFT for 210-MHz Input Signal
ADS54J69 D006_SBAS713.gif
SNR = 70.5 dBFS; SFDR = 86 dBc; SINAD = 70.4 dBFS;
THD = 85 dBc; HD2 = –86 dBc; HD3 = –96 dBc;
IL spur = 98 dBc; non HD2, HD3 spur = 98 dBc
Figure 8. FFT for 370-MHz Input Signal
ADS54J69 D008_SBAS713.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS,
IMD = 86 dBFS
Figure 10. FFT for Two-Tone Input Signal (–7 dBFS)
ADS54J69 D010_SBAS713.gif
fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –7 dBFS,
IMD = 79 dBFS
Figure 12. FFT for Two-Tone Input Signal (–7 dBFS)
ADS54J69 D012_SBAS713.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –10 dBFS,
IMD = 78 dBFS
Figure 14. FFT for Two-Tone Input Signal (–10 dBFS)
ADS54J69 D014_SBAS713.gif
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 16. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
ADS54J69 D016_SBAS713.gif
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 18. Intermodulation Distortion vs
Input Amplitude (465 MHz and 470 MHz)
ADS54J69 D018_SBAS713.gif
Figure 20. IL Spur vs Input Frequency
ADS54J69 D020_SBAS713.gif
fIN = 185 MHz
Figure 22. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADS54J69 D022_SBAS713.gif
fIN = 300 MHz
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADS54J69 D024_SBAS713.gif
fIN = 185 MHz
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADS54J69 D026_SBAS713.gif
fIN = 300 MHz
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADS54J69 D028_SBAS713.gif
fIN = 185 MHz
Figure 30. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
ADS54J69 D030_SBAS713.gif
fIN = 300 MHz
Figure 32. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
ADS54J69 D032_SBAS713.gif
Figure 34. Signal-to-Noise Ratio vs
Gain and Input Frequency
ADS54J69 D034_SBAS713.gif
Figure 36. Second-Order Harmonic Distortion vs
Gain and Input Frequency
ADS54J69 D036_SBAS713.gif
Figure 38. IL Spur vs Gain and Input Frequency
ADS54J69 D038_SBAS713.gif
fIN = 310 MHz
Figure 40. Performance vs Amplitude
ADS54J69 D040_SBAS713.gif
fIN = 310 MHz
Figure 42. IL Spur vs Amplitude
ADS54J69 D042_SBAS713.gif
fIN = 310 MHz
Figure 44. Performance vs Differential Clock Amplitude
ADS54J69 D044_SBAS713.gif
fIN = 300 MHz
Figure 46. Performance vs Input Clock Duty Cycle
ADS54J69 D046_SBAS713.gif
fIN = 185 MHz
Figure 48. Power-Supply Rejection Ratio vs
Noise Signal Frequency
ADS54J69 D048_SBAS713.gif
fIN = 185 MHz
Figure 50. Common-Mode Rejection Ratio vs
Common-Mode Signal Frequency
ADS54J69 D050_SBAS713.gif
Figure 52. Power Consumption vs Sampling Speed
ADS54J69 D052_SBAS713.gif
Figure 54. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 300 MSPS)
ADS54J69 D054_SBAS713.gif
Figure 56. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 350 MSPS)
ADS54J69 D056_SBAS713.gif
Figure 58. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 400 MSPS)