SNAS304H January   2006  – April 2016 ADC121S101 , ADC121S101-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: ADC121S101
    3. 7.3 ESD Ratings: ADC121S101-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Determining Throughput
      2. 8.3.2 ADC Transfer Function
      3. 8.3.3 Analog Inputs
      4. 8.3.4 Digital Inputs and Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
    2. 10.2 Power Supply Noise Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

NGF Package
6-Pin WSON
Top View
DBV Package
6-Pin SOT-23
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 VA P Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin.
2 GND G The ground return for the supply and signals.
3 VIN I Analog input. This signal can range from 0 V to VA.
4 SCLK I Digital clock input. This clock directly controls the conversion and readout processes.
5 SDATA O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
6 CS I Chip select. On the falling edge of CS, a conversion process begins.
PAD GND G For package suffix CISD(X) only. TI recommends connecting the center pad to ground.
(1) G = Ground, I = Input, O = Output, P = Power