DLPDLCR160CPEVM-FW

Overview

The firmware is primarily intended for the DLPDLCR160CPEVM:

• DMD: DLP160CP
• Controller: DLPC3421
• PMIC: DLPA2005
• Illumination: 3-LED (RGB)
• I2C address: 0x36
• DMD pin mapping: Option 2

Known Limitations

• Artifact issues if Splash image 0 is saved as YCrCb format.
• Linearity issues on ramp Test Pattern Generator.
• Image Freeze command may disable after source select command is sent.
• External video requires double execution for reliable operation.
• Image scaling artifact when image crop set to 320x180.
• I2C speed is limited to 100 KHz
• Single Buffer Mode has various limitations. See Single Buffer Mode Documentation for more information.
• Manual Idle mode may be unsuitable for some situations as it takes time to enter and exit the mode. There are additional limitations of sending commands when in idle mode. See Idle Mode Documentation for more information.
• DSI support for 320 x 180 up to 60Hz
• DSI HS_PREP >110ns induces artifacts
• Splash screen requires double execution for reliable operation
• When operating with low IDAC values (i.e. low LED currents), non-linearities may occur with the LED currents. This could be optimized with a system level design (i.e. optimizing passives) or by avoiding operation in this region
• The DMD may not be properly parked if the controller is interrupted during its startup routine.