SN65LVDS20EVM
SN65LVDS20 评估模块
SN65LVDS20EVM
概述
This Evaluation Module (EVM) facilitates the experimental testing of the Texas Instruments SN65LVDS20 Repeater/Translator silicon device.This device accepts low-voltage PECL input levels and Translates them to LVDS output levels as defined by TIA/EIA-644-A standard.
The device operates at rates to 4Gbps or clock rates to 2 GHz at either 3.3 V or 2.5 V supply operation, with less than 45 ps of total jitter.The device output can be disabled to the high impedance state by applying a logic High level to the EN bar pin.
This device also provides a voltage reference output (Vbb) of typically 1.35 V below Vcc for use in receiving single-ended PECL input signals.
LVDS、M-LVDS 和 PECL IC
技术文档
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类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | Translator/Oscillator Buffer EVM (Rev. A) | 2004年 9月 17日 | |||
证书 | SN65LVDS20EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 |