PMP21619
适用于 2.7V 60A 电信应用的双相紧凑型参考设计
PMP21619
概述
This reference design uses only 2 ICs in a stacked configuration to provide 2.7 V at 60 A in a compact form factor. Both an all ceramics output capacitors version and a low ESR polymer output capacitors version were demonstrated to meet requirement of less than 3% undershoot for a step load from 2 A to 60 A in less than 1 microsecond. Internal compensation simplifies the design process. Design includes on-board high speed dynamic load tester, output ripple probe interface and test points for a stability analyzer.
特性
- 2.7 V at 60 A with only two 5-mm by 7-mm ICs
- Meets less than 3% voltage undershoot for step load from 2 A to 60 A in under 1 microsecond
- Verified to meet this performance with either all ceramic out capacitors or with polymer output capacitors
- Rich test interface, including on-board, high speed dynamic load
| 输出电压选项 | PMP21619.1 |
|---|---|
| Vin (Min) (V) | 10 |
| Vin (Max) (V) | 14 |
| Vout (Nom) (V) | 2.7 |
| Iout (Max) (A) | 60 |
| Output Power (W) | 162 |
| Isolated/Non-Isolated | Non-Isolated |
| Input Type | DC |
| Topology | Multiphase |
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| 类型 | 标题 | 下载最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 测试报告 | Dual-phase compact reference design for 2.7 V 60 A for telecommunications | 2019年 2月 6日 |