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TXGS441-SEP

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Radiation-tolerant, 4 bit, fixed direction 3/1 ground level translator

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TXGS441-SEP

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產品詳細資料

Rating Space Ground offset voltage (max) (V) 40 Bits (#) 4 Topology Push-Pull Applications GPIO, I2S, PCM, SPI Forward/reverse channels 3 forward / 1 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 1000 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Output type 3-State Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
Rating Space Ground offset voltage (max) (V) 40 Bits (#) 4 Topology Push-Pull Applications GPIO, I2S, PCM, SPI Forward/reverse channels 3 forward / 1 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 1000 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Output type 3-State Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
SOT-23-THN (DYY) 14 13.692 mm² (4.2 mm × 3.26 mm)

  • VID: TBD

  • Radiation tolerant:

    • Single event latch-up (SEL) immune up to 43 MeV-cm2 /mg at 125°C

    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)

  • Supports DC ground shifts up to ±40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
  • Greater than 250Mbps
  • Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –55°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000V human-body model
    • 500V charged-device model
  • Small SOT-24 (DYY-14) package

  • VID: TBD

  • Radiation tolerant:

    • Single event latch-up (SEL) immune up to 43 MeV-cm2 /mg at 125°C

    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)

  • Supports DC ground shifts up to ±40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
  • Greater than 250Mbps
  • Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –55°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000V human-body model
    • 500V charged-device model
  • Small SOT-24 (DYY-14) package

The TXGS441-SEP is a ±40V, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXGS441-SEP family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is 45nA when VCC to GND is shorted.

The TXGS441-SEP device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can suppress noise levels of 80VPP up to 5MHz (Figure 7-3). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.

The TXGS441-SEP is a ±40V, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXGS441-SEP family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is 45nA when VCC to GND is shorted.

The TXGS441-SEP device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can suppress noise levels of 80VPP up to 5MHz (Figure 7-3). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TXGS441-SEP Radiation Tolerant 4-bit, ±40V Ground-Level Translator datasheet PDF | HTML 2025/6/10
* 輻射及可靠性報告 TXGS441-SEP Production Flow and Reliability Report PDF | HTML 2026/5/8
Application brief Solving Ground Shift Issues in Phase Array Satellites PDF | HTML 2026/7/30
Application brief Top Questions about Ground-Level Translators PDF | HTML 2026/5/27

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