TXG4041
- Supports DC ground shifts up to 40V
- AC Noise Rejection of 80VPP up to 5MHz
- CMTI of 1kV/µs
- Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
- Greater than 250Mbps
- Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
- Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
- 4, 2, 1 channel devices available
- Two device variants:
- TXG4041: 3 forward, 1 reverse
- TXG4042: 2 forward, 2 reverse
- Supports VCC disconnect feature (I/Os are forced into high-Z)
- Schmitt-trigger inputs allows for slow and noisy signals
- Inputs with integrated static pull-down resistors prevent channels from floating
- Operating temperature from –40°C to +125°C
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 4000V human-body model
- 500V charged-device model
- Package options provided:
- RUC (X2QFN-14)
- DYY (SOT-14)
- DBQ (QSOP-16)
The TXG404x is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that supports both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG404x family solves the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.
VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is <45nA when VCC to GND is shorted.
The TXG404x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency, and channel-to-channel skew. The device supresses noise levels of 80VPP up to 5MHz (Figure 7-5). TXG404x can support multiple interfaces such as SPI, UART, GPIO, and I2S.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TXG404x 4-bit , ± 40V Ground-Level Translator datasheet (Rev. A) | PDF | HTML | 2025/9/5 | ||
| Application brief | Solving Ground Shift Issues in Phase Array Satellites | PDF | HTML | 2026/7/30 | |||
| Application brief | Top Questions about Ground-Level Translators | PDF | HTML | 2026/5/27 | |||
| 技術文章 | 接地電位不均？以新型的接地電平轉換器解決偏移挑戰 (Rev. A) | PDF | HTML | Download English Version (Rev.A) | PDF | HTML | 2025/6/5 | |
| Application brief | Not All Grounds Are 0V | PDF | HTML | 2025/5/21 | |||
| Product overview | TI's Latest Ground-Level Translators | PDF | HTML | 2025/5/7 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
TXG-4CH-EVM — 適用於 4 通道接地位準轉換器的 TXG 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23-THN (DYY) | 14 | Ultra Librarian |
| SSOP (DBQ) | 16 | Ultra Librarian |