TS3DDR4000
- Wide VDD Range: 2.375 V – 3.6 V
- High Bandwidth: 5.6 GHz Typical (single-ended); 6.0 GHz Typical (differential)
- Low Switch On-Resistance (RON): 8 Ω Typical
- Low Bit-to-Bit Skew: 3ps Typical; 6ps Max across All Channels
- Low Crosstalk: –34 dB Typical at 1067 MHz
- Low Operating Current: 40 µA Typical
- Low-Power Mode with Low Current Consumption: 2 µA Typical
- IOFF Protection Prevents Current Leakage in Powered Down State (VDD = 0 V)
- Supports POD_12, SSTL_12, SSTL_15 and SSTL_18 Signaling
- ESD Performance:
- 3-kV Human Body Model (A114B, Class II)
- 1-kV Charged Device Model (C101)
- 8 mm x 3 mm 48-balls 0.65-mm Pitch ZBA Package
The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The A port can be switched to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and DDR4 memory bus systems, the TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (single-ended –3dB bandwidth at 5.6 GHz), low insertion loss at low frequency, and very low propagation delay. The TS3DDR4000 is 1.8 V logic compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-power mode, in which all channels become high-Z and the device consumes minimal power.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TS3DDR4000 12-bits 1:2 high speed DDR2/DDR3/DDR4 switch/multiplexer datasheet (Rev. C) | PDF | HTML | 2019/3/18 | ||
| Product overview | Mipi Switches | PDF | HTML | 2022/1/14 | |||
| 技術文章 | Memory switches bring reliability and speed to clouding computing | PDF | HTML | 2016/1/5 |
設計與開發
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TS3DDR4000-EVM — TS3DDR4000 評估模組
TS3DDR4000-EVM 這款評估模組適用於 TI 的 12 位元高速 DDR2、DDR3 及 DDR4 開關/多工器。 此模組可讓您輕鬆評估功能切換和邏輯實作。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (ZBA) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。