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線性與低壓差 (LDO) 穩壓器

TPS7A92

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TPS7A96 現行 2-A、超低雜訊、超高 PSRR 射頻電壓穩壓器 Lower noise with improved PSRR and adjustable current limit

TPS7A92

現行
產品規格表 立即訂購

產品詳細資料

Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.4 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.2 Vout (min) (V) 0.8 Noise (µVrms) 4.7 PSRR at 100 KHz (dB) 48 Iq (typ) (mA) 2.1 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 56.9 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 260 Operating temperature range (°C) -40 to 125
Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.4 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.2 Vout (min) (V) 0.8 Noise (µVrms) 4.7 PSRR at 100 KHz (dB) 48 Iq (typ) (mA) 2.1 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 56.9 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 260 Operating temperature range (°C) -40 to 125
WSON (DSK) 10 6.25 mm² (2.5 mm × 2.5 mm)
  • 1.0% accuracy over line, load, and temperature
  • Low output noise: 4.6µVRMS (10Hz – 100kHz)
  • Low dropout: 180mV (typical) at 2A
  • Wide input voltage range: 1.4V to 6.5V
  • Wide output voltage range: 0.8V to 5.2V
  • High power-supply rejection ratio (PSRR):
    • 60dB at DC
    • 40dB at 100kHz
    • 40dB at 1MHz
  • Fast transient response
  • Adjustable start-up in-rush control with selectable soft-start charging current
  • Open-drain power-good (PG) output
  • RθJC = 3.2°C/W
  • Stable with a 22µF or larger ceramic output capacitor
  • 2.5mm × 2.5mm, 10-pin WSON package
  • 1.0% accuracy over line, load, and temperature
  • Low output noise: 4.6µVRMS (10Hz – 100kHz)
  • Low dropout: 180mV (typical) at 2A
  • Wide input voltage range: 1.4V to 6.5V
  • Wide output voltage range: 0.8V to 5.2V
  • High power-supply rejection ratio (PSRR):
    • 60dB at DC
    • 40dB at 100kHz
    • 40dB at 1MHz
  • Fast transient response
  • Adjustable start-up in-rush control with selectable soft-start charging current
  • Open-drain power-good (PG) output
  • RθJC = 3.2°C/W
  • Stable with a 22µF or larger ceramic output capacitor
  • 2.5mm × 2.5mm, 10-pin WSON package

The TPS7A92 is a low-noise (4.6µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2A with only 180mV of maximum dropout.

The TPS7A92 output is adjustable with external resistors from 0.8V to 5.2V. The TPS7A92 wide input voltage range supports operation as low as 1.4V and up to 6.5V.

With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A92 is designed for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].

The TPS7A92 is designed to power noise-sensitive components such as components found in high-speed communication, video, medical, or test and measurement applications. The very low 4.6µVRMS output noise and wideband PSRR (40dB at 1MHz) minimizes phase noise and clock jitter. These features maximize performance of clocking devices, ADCs, and DACs.

The TPS7A92 is a low-noise (4.6µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2A with only 180mV of maximum dropout.

The TPS7A92 output is adjustable with external resistors from 0.8V to 5.2V. The TPS7A92 wide input voltage range supports operation as low as 1.4V and up to 6.5V.

With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A92 is designed for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].

The TPS7A92 is designed to power noise-sensitive components such as components found in high-speed communication, video, medical, or test and measurement applications. The very low 4.6µVRMS output noise and wideband PSRR (40dB at 1MHz) minimizes phase noise and clock jitter. These features maximize performance of clocking devices, ADCs, and DACs.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS7A92 2A, High-Accuracy, Low-Noise LDO Voltage Regulator datasheet (Rev. C) PDF | HTML 2026/9/24
白皮書 Demystifying LDO Turn-On (Start-Up) Time (Rev. B) PDF | HTML 2026/3/10
白皮書 Reduce System Noise Using Parallel LDOs PDF | HTML 2025/11/3
白皮書 Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022/12/14
白皮書 Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022/12/13

設計與開發

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開發板

TPS7A91EVM-831 — 適用於類比的 TPS7A91 1A 低雜訊低輸入電壓低壓差 (LDO) 穩壓器評估模組

TPS7A91EVM-831 評估模組採用典型配置設計，用於評估 TPS7A91 1A 高準確度低壓差電壓穩壓器的運作與性能。EVM 電路板主要配置爲參考設計，可供需要高達 1 A 動態負載電流的工程應用。
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TPS7A9201 PSpice Transient Model

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模擬型號

TPS7A9201 Unencrypted PSpice Transient Model

SBVM668.ZIP (2 KB) - PSpice 模型
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計算工具

PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator

並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。

在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。

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