TPS7A91
- 1.0% Accuracy Over Line, Load, and Temperature
- Low Output Noise: 4.7 µVRMS (10 Hz–100 kHz)
- Low Dropout: 200 mV (max) at 1 A
- Wide Input Voltage Range: 1.4 V to 6.5 V
- Wide Output Voltage Range: 0.8 V to 5.2 V
- High Power-Supply Ripple Rejection (PSRR):
- 70 dB at DC
- 40 dB at 100 kHz
- 40 dB at 1 MHz
- Fast Transient Response
- Adjustable Start-Up In-Rush Control with Selectable Soft-Start Charging Current
- Open-Drain Power-Good (PG) Output
- 2.5-mm × 2.5-mm, 10-Pin SON Package
The TPS7A91 is a low-noise (4.7 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 1 A with only 200 mV of maximum dropout.
The TPS7A91 output is adjustable with external resistors from 0.8 V to 5.2 V. The TPS7A91 wide input-voltage range supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A91 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A91 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 4.7-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize performance of clocking devices, ADCs, and DACs.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS7A91 1-A, High-Accuracy, Low-Noise LDO Voltage Regulator datasheet | PDF | HTML | 2016/12/13 | ||
| 白皮書 | Demystifying LDO Turn-On (Start-Up) Time (Rev. B) | PDF | HTML | 2026/3/10 | |||
| 白皮書 | Reduce System Noise Using Parallel LDOs | PDF | HTML | 2025/11/3 | |||
| 白皮書 | Parallel LDO Architecture Design Using Ballast Resistors | PDF | HTML | 2022/12/14 | |||
| 白皮書 | Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast | PDF | HTML | 2022/12/13 | |||
| 技術文章 | LDO basics: noise – how a feed-forward capacitor improves system performance | PDF | HTML | 2017/7/25 | |||
| 技術文章 | LDO basics: noise – how a noise-reduction pin improves system performance | PDF | HTML | 2017/6/14 |
設計與開發
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TPS7A91EVM-831 — 適用於類比的 TPS7A91 1A 低雜訊低輸入電壓低壓差 (LDO) 穩壓器評估模組
PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator
並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。
在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WSON (DSK) | 10 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。