TPS794
- 250mA low-dropout regulator with enable
- Available in fixed and adjustable versions
- High PSRR: 60dB at 10kHz
- Fast start-up
- Excellent load, line transient response
- Very low dropout voltage: 155mV(typ) at full load
- Available in HVSSOP-8 and SOT223-6 packages
The TPS794 low-dropout (LDO) linear voltage regulator features high power-supply rejection ratio (PSRR), low-noise, fast start-up, and excellent line and load transient responses. Each device in the family is stable with a small 2.2µF ceramic capacitor on the output. The TPS794 offers low dropout voltages, 155mV (typ) at 250mA.Applications with analog components that are noise-sensitive, such as portable RF electronics, benefit from the high PSRR and low noise features as well as the fast response time.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS794 250mA, Low-Dropout Linear Regulator datasheet (Rev. F) | PDF | HTML | 2025/12/19 | ||
| 應用說明 | LDO Noise Demystified (Rev. B) | PDF | HTML | 2020/8/18 | |||
| 應用說明 | PowerPAD™ Thermally Enhanced Package (Rev. H) | 2018/7/6 | ||||
| 應用說明 | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017/8/9 | |||
| 測試報告 | TI Power Reference Design for Xilinx® Artix®-7 (AC701) | 2014/5/12 | ||||
| 使用指南 | PMP7977 User's Guide | 2013/9/11 | ||||
| 應用說明 | Using 3.3-V Signals for Spartan-3 Configuration and JTAG Ports (Rev. A) | 2004/4/13 | ||||
| 使用指南 | DEM-SOT223LDO Demonstration Fixture | 2003/10/15 |
設計與開發
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DEM-SOT223LDO — 採用 SOT223 (DCQ) 封裝與最大正輸出 LDO 相容的 DEM-SOT223LDO
The Texas Instruments DEM-SOT223LDO demonstration module (DEM) helps designers evaluate the operation and performance of Texas Instruments low-dropout regulators (LDOs). This module is compatible with most positive output LDOs offered in the SOT223 (DCQ) package.
PMP7977 — 具有 PMBus 電源管理的 Xilinx Artix 7 FPGA 參考設計
The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HVSSOP (DGN) | 8 | Ultra Librarian |
| SOT-223 (DCQ) | 6 | Ultra Librarian |
訂購與品質
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