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TPS51116

現行

完整的 DDR、DDR2、DDR3、DDR3L、LPDDR3 和 DDR4 電源解決方案同步降壓控制器，3A LDO

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產品規格表

TPS51116

現行
產品規格表 立即訂購

產品詳細資料

Product type DDR Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.8 DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Product type DDR Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.8 DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
HTSSOP (PWP) 20 41.6 mm² (6.5 mm × 6.4 mm) VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS51116 Complete DDR, DDR2, DDR3, DDR3L, LPDDR3 and DDR4 Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference datasheet (Rev. J) PDF | HTML 2017/11/16
類比設計期刊 Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 2023/8/29
應用說明 DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/7/9
選擇指南 Power Management Guide 2018 (Rev. R) 2018/6/25
技術文章 Design advantage of D-CAP control topology PDF | HTML 2017/4/13
技術文章 D-CAP3 – A sequel better than the original PDF | HTML 2015/5/7
更多文件說明 Computing DDR DC-DC Power Solutions 2012/8/22
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應用說明 Intel EP80579 Tolopai System-on-Chip Reference Design 2010/7/21
應用說明 Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010/4/28
應用說明 Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010/4/20
應用說明 Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010/3/31
應用說明 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010/3/26
應用說明 TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010/3/26
應用說明 Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010/3/26
應用說明 Cyclone™ III FPGA Starter Kit Power Reference Design 2008/3/27
應用說明 DDR2 Power Solutions for Notebooks 2004/5/24

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TPS51116EVM-001 — TPS51116 記憶體功率解決方案，同步降壓控制器評估模組

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

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模擬型號

TPS51116 PSpice Transient Model (Rev. B)

SLIM076 (96 KB) - PSpice 模型
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TPS51116 TINA-TI Transient Reference Design

SLUM166.TSC (224 KB) - TINA-TI 參考設計
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TPS51116 TINA-TI Transient Spice Model

SLUM167.ZIP (58 KB) - TINA-TI Spice 模型
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HTSSOP (PWP) 20 Ultra Librarian
VQFN (RGE) 24 Ultra Librarian
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