產品詳細資料

Configuration 1:1 SPST Number of channels 3 Power supply voltage - single (V) 0.8, 1.2, 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 10.5 ON-state leakage current (max) (µA) 5 Supply current (typ) (µA) 0.07 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (A) 0.064 Rating Catalog Drain supply voltage (max) (V) 5
Configuration 1:1 SPST Number of channels 3 Power supply voltage - single (V) 0.8, 1.2, 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 10.5 ON-state leakage current (max) (µA) 5 Supply current (typ) (µA) 0.07 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (A) 0.064 Rating Catalog Drain supply voltage (max) (V) 5
SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm)
  • Designed to be used in voltage-limiting applications
  • 3.5-ω on-state connection between ports A and B
  • Flow-through pinout for ease of printed circuit board trace routing
  • Direct interface with GTL+ levels
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • Designed to be used in voltage-limiting applications
  • 3.5-ω on-state connection between ports A and B
  • Flow-through pinout for ease of printed circuit board trace routing
  • Direct interface with GTL+ levels
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

The SN74TVC3306 device provides three parallel NMOS pass transistors with a common unbuffered gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots.

The SN74TVC3306 device provides three parallel NMOS pass transistors with a common unbuffered gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74TVC3306 Dual Voltage Clamp datasheet (Rev. E) PDF | HTML 2023/9/5
應用說明 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/6/2
應用說明 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/1
更多文件說明 I2C and Serial Bus Devices Application Clip 2003/7/10

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DIP-ADAPTER-EVM — DIP 轉接器評估模組

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

EVM-LEADED1 板可用於快速測試和搭建 TI 常見的有引腳封裝  此電路板具備板上配置,可將 TI 的 D、DBQ、DCT、DCU、DDF、DGS、DGV 和 PW 表面黏著封裝轉換為 100mil DIP 排針。     

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模擬型號

HSPICE Model of SN74TVC3306

SCEJ172.ZIP (81 KB) - HSpice 模型
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模擬型號

SN74TVC3306 IBIS Model (Rev. A)

SCDM002 (125 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

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