產品詳細資料

Bits (#) 8 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Integrated pulldown resistors, Output enable, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 8 Technology family LXC Supply current (max) (mA) 0.012 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 8 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Integrated pulldown resistors, Output enable, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 8 Technology family LXC Supply current (max) (mA) 0.012 Rating Catalog Operating temperature range (°C) -40 to 125
VQFN (RHL) 24 19.25 mm² (5.5 mm × 3.5 mm) TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm) VSSOP (DGS) 24 29.89 mm² (6.1 mm × 4.9 mm)
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • I/Os with integrated dynamic pull-down resistors help reduce external component count
  • Control inputs with integrated static pull-down resistors allow for floating control inputs
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption:
    • 4-µA maximum (25°C)
    • 12-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/Os get pulled-down and then become high-impedance
  • Ioff supports partial-power-down mode operation
  • Compatible with LVC family level shifters
  • Control logic (DIR and OE) are referenced to VCCA
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model
    • 1000-V Charged-Device Model
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • I/Os with integrated dynamic pull-down resistors help reduce external component count
  • Control inputs with integrated static pull-down resistors allow for floating control inputs
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption:
    • 4-µA maximum (25°C)
    • 12-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/Os get pulled-down and then become high-impedance
  • Ioff supports partial-power-down mode operation
  • Compatible with LVC family level shifters
  • Control logic (DIR and OE) are referenced to VCCA
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model
    • 1000-V Charged-Device Model

The SN74LXC8T245 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

The SN74LXC8T245 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

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模擬型號

SN74LXC8T245 IBIS model

SCEM785.ZIP (57 KB) - IBIS 模型
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VQFN (RHL) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
VSSOP (DGS) 24 Ultra Librarian

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