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正反器、鎖存器和暫存器
D 型正反器

SN74LVTH273

現行

具有清除功能的 3.3-V ABT 八路 D 型正反器

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產品規格表

SN74LVTH273

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 8 Technology family LVT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family LVT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
        <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Buffered Clock and Direct-Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
        <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Buffered Clock and Direct-Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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SN74HCT273 現行 具有清除功能的八路 D 型正反器 Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN54LVTH273, SN74LVTH273 datasheet (Rev. M) 2003/10/13
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
應用說明 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018/9/17

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模擬型號

HSPICE Model of SN74LVTH273

SCEJ174.ZIP (103 KB) - HSpice 模型
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模擬型號

SN74LVTH273 IBIS Model (Rev. B)

SCBM055A (119 KB) - IBIS 模型
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TSSOP (PW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
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