SN74LVC828A

現行

具有 3 態輸出的 10 通道 1.65-V 至 3.6-V 逆變器

立即訂購

產品規格表

document-pdfAcrobat SN74LVC828A datasheet (Rev. H) (英文)

SN74LVC828A

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

10

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LVC

Number of channels

10

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

24

49.92 mm² (7.8 mm × 6.4 mm)

SOIC (DW)

24

159.65 mm² (15.5 mm × 10.3 mm)

TVSOP (DGV)

24

32 mm² (5 mm × 6.4 mm)

Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.7 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.7 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2)\ input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at its outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2)\ input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at its outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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