SN74LVC3G04

現行

3 通道、1.65-V 至 5.5-V 逆變器

立即訂購

產品規格表

document-pdfAcrobat Triple Inverter Gate, SN74LVC3G04 datasheet (Rev. L) (英文)

SN74LVC3G04

現行

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This triple inverter is designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G04 device performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This triple inverter is designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G04 device performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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