SN74LVC373A
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Supports Mixed-Mode Signal Operation
on All Ports
(5-V Input/Output Voltage With 3.3-V VCC) - Ioff Supports Live-Insertion, Partial-Power-Down Mode,
and Back-Drive Protection - Latch-Up Performance Exceeds 250 mA Per
JESD 17 - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- On Products Compliant to MIL-PRF-38535, All
Parameters Are Tested Unless Otherwise Noted.
On All Other Products, Production Processing
Does Not Necessarily Include Testing of All
Parameters.
The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
For all available packages, see the orderable addendum at the end of the data sheet.技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. T) | PDF | HTML | 2013/11/21 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
開發板
14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組
14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用於支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
| SOIC (DW) | 20 | Ultra Librarian |
| VQFN (RGY) | 20 | Ultra Librarian |
| SOP (NS) | 20 | Ultra Librarian |
| TVSOP (DGV) | 20 | Ultra Librarian |
| SSOP (DB) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |