SN74LVC2G32-Q1

現行

車用 2 通道、2 輸入、1.65-V 至 5.5-V 32-mA 驅動強度 OR 閘

立即訂購

產品規格表

document-pdfAcrobat Dual 2-input Positive OR gate datasheet (英文)

SN74LVC2G32-Q1

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to 125°C
  Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
Inputs Accept Voltages to 5.5 V
Max Propagation (Delay) Time of 3.8 ns at 3.3 V
Low Power Consumption, 10-µA Max Supply Current
±24-mA Output Drive at 3.3 V
Typical Voltage Output Low Peak (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical Voltage Output High Valley (V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off State Current Supports Partial-Power-Down Mode
Operation

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to 125°C
  Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
Inputs Accept Voltages to 5.5 V
Max Propagation (Delay) Time of 3.8 ns at 3.3 V
Low Power Consumption, 10-µA Max Supply Current
±24-mA Output Drive at 3.3 V
Typical Voltage Output Low Peak (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical Voltage Output High Valley (V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off State Current Supports Partial-Power-Down Mode
Operation

This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.

The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.

The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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