SN74LVC2G32
- Available in the Texas Instruments
NanoFree™ Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Maximum tpd of 3.8 ns at 3.3 V
- Low Power Consumption, 10-µA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection - Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the VCC
Level - Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G32 device performs the Boolean function Y = A + B or Y = A • B in positive logic.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LVC2G32 Dual 2-Input Positive-OR Gate datasheet (Rev. N) | PDF | HTML | 2015/9/18 | ||
| Application brief | Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A) | PDF | HTML | 2022/9/29 |
設計與開發
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開發板
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南:
PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DCT) | 8 | Ultra Librarian |
| DSBGA (YZP) | 8 | Ultra Librarian |
| VSSOP (DCU) | 8 | Ultra Librarian |