SN74LVC2G02

現行

2 通道、2 輸入、1.65-V 至 5.5-V NOR 閘

立即訂購

產品規格表

document-pdfAcrobat Dual 2-Input Positive-NOR Gate, SN74LVC2G02 datasheet (Rev. N) (英文) PDF | HTML

SN74LVC2G02

現行

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

Available in the Texas Instruments
NanoFree™ package
Supports 5-V V_CC operation
Inputs accept voltages to 5.5 V
Max t_pd of 4.9 ns at 3.3 V
Low power consumption, 10-µA Max I_CC
±24-mA Output drive at 3.3 V
Typical V_OLP (output ground bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (output V_OH undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off supports partial-power-down mode operation
Latch-up performance exceeds 100 mA er JESD 78, class II
ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 1000-V Charged-device model (C101)

Available in the Texas Instruments
NanoFree™ package
Supports 5-V V_CC operation
Inputs accept voltages to 5.5 V
Max t_pd of 4.9 ns at 3.3 V
Low power consumption, 10-µA Max I_CC
±24-mA Output drive at 3.3 V
Typical V_OLP (output ground bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (output V_OH undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off supports partial-power-down mode operation
Latch-up performance exceeds 100 mA er JESD 78, class II
ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 1000-V Charged-device model (C101)

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G02 device performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G02 device performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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