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邏輯和電壓轉換
可配置且可編程邏輯 IC
可配置閘

SN74LVC1G97

現行

可配置多功能閘

立即訂購
產品規格表

SN74LVC1G97

現行
立即訂購

產品詳細資料

Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm)
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree&traDe; Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Choose From Nine Specific Logic Functions
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree&traDe; Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Choose From Nine Specific Logic Functions

The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74AUP1G97 現行 低功耗可配置多功能閘 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LVC1G97 Configurable Multiple-Function Gate datasheet (Rev. N) PDF | HTML 2017/1/4
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025/4/17
Application brief Utilizing Configurable Logic in System Design PDF | HTML 2024/10/30
更多文件說明 SN74LVC1G97 and SN74LVC1G98 Product Clip (Rev. A) 2004/7/13

設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM

支援任何具 DTT、DRY、DPW、DTM、DQE、DQM、DSF 或 DTQ 封裝的邏輯或轉換裝置之通用 EVM。可實現靈活評估的電路板設計。

使用指南: PDF | HTML
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模擬型號

SN74LVC1G97 IBIS Model (Rev. A)

SCEM306 (241 KB) - IBIS 模型
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參考設計

TIDA-00862 — RS-485 雙線路全雙工參考設計

該設計透過匯流排競爭技術，僅需單對導線即可實現全雙工 RS-485 通訊，取代傳統四線架構。透過在匯流排線路上串接小阻值電阻來限制電流，即可實現三態差動匯流排架構，此時採用 SN65HVD96 SymPol 收發器即可檢測匯流排競爭狀態。透過簡易數位邏輯與類比濾波技術，即可實現雙收發器互相驅動與同步接收，無需額外增加 2 條匯流排線路。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
DSBGA (YZP) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
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