SN74LVC1G80

現行

單路正緣觸發 D 型正反器

立即訂購

產品規格表

document-pdfAcrobat SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. S) (英文) PDF | HTML

SN74LVC1G80

現行

立即訂購

產品詳細資料

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

DSBGA (YZP)

5

2.1875 mm² (— mm × — mm)

SOT-23 (DBV)

5

8.12 mm² (2.9 mm × 2.8 mm)

Available in the Texas Instruments NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 4.2 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 4.2 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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SN74AUP1G80

現行

低功耗單路正緣觸發 D 型正反器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. S)	PDF \| HTML		2016/11/30
	應用說明	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML		2022/12/15