SN74LVC1G132

現行

具有施密特觸發器輸入的單路 2 輸入、1.65-V 至 5.5-V NAND 閘

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產品規格表

document-pdfAcrobat SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D) (英文) PDF | HTML

SN74LVC1G132

現行

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Schmitt-Trigger

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Schmitt-Trigger

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

SOT-23 (DBV)

5

8.12 mm² (2.9 mm × 2.8 mm)

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.3 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Partial-Power-Down Mode Operation

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.3 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Partial-Power-Down Mode Operation

The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V V_CC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.

Because of Schmitt action, this device has different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V V_CC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.

Because of Schmitt action, this device has different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D)	PDF \| HTML		2017/6/8

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模擬型號

SN74LVC1G132 Behavioral SPICE Model

SCEM636.ZIP (7 KB) - PSpice 模型

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模擬型號

SN74LVC1G132 IBIS Model (Rev. A)

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SN74LVC1G132

具有施密特觸發器輸入的單路 2 輸入、1.65-V 至 5.5-V NAND 閘

SN74LVC1G132

產品詳細資料

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針腳對針腳的功能與所比較的裝置相同。

功能相似於所比較的產品。

技術文件

設計與開發

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

SN74LVC1G132 Behavioral SPICE Model

SN74LVC1G132 IBIS Model (Rev. A)

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