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SN74LVC1G123

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產品詳細資料

Number of channels 1 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 1 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
DSBGA (YZP) 8 2.8125 mm² (— mm × — mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LVC1G123 Single Retriggerable Monostable Multivibrator With Schmitt-Trigger Inputs datasheet (Rev. E) PDF | HTML 2024/3/1
Product overview Configurable Timed Reset Using Discrete Logic (Rev. A) PDF | HTML 2023/5/2
應用說明 The Davies Sinusoidal Generator PDF | HTML 2022/10/31
應用說明 Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 2020/3/13

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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模擬型號

HSPICE Model for SN74LVC1G123

SCEJ262.ZIP (98 KB) - HSpice 模型
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模擬型號

SN74LVC1G123 IBIS Model

SCEM427.ZIP (45 KB) - IBIS 模型
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參考設計

TIDA-060008 — 用於將 RS-232 訊號轉換爲 RS-485 訊號的參考設計

此參考設計提供將 RS-232 訊號轉換為 RS-485 訊號的電路。這允許長距離通訊,因 RS-232 支援的範圍通常小於 50 英呎,而 RS-485 的範圍則可超過 1000 英呎。此設計實施雙向半雙工通訊,且無任何軟體干擾。
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參考設計

TIDEP0056 — 在 BeagleBone Black 上使用 PRU-ICSS 進行熱感列印的參考設計

可編程即時單元 — 工業通訊子系統 (PRU-ICSS) 是 AM335x SoC 的多用途元件,即使在執行非確定性作業系統,也可實現即時、確定性且快速的 GPIO 控制。此參考設計提供 PRU-ICSS 的具體使用案例與實作,可直接控制熱敏式印表機模組。  包含適用於 ARM 至 PRU 通訊的 C 程式碼範例,可驅動熱敏列印頭元件和步進馬達的即時 GPIO 針腳控制,以及 Pinmux 配置。

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DSBGA (YZP) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian

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