SN74LVC00A
- ESD protection exceeds JESD 22
- 2000V Human-Body Model
- 1000V Charged-Device Model
- SN74LVC00A operates from 1.65V to 3.6V
- SN54LVC00A operates from 2V to 3.6V
- SNx4LVC00A specified from –40°C to +85°C and –40°C to +125°C
- SN54LVC00A specified from –55°C to +125°C
- Inputs accept voltages to 5.5V
- Max tpd of 4.3ns at 3.3V
- Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
- Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
- Latch-up performance exceeds 250 mA per JESD 17
- On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7V to 3.6V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.
The SNx4LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4LVC00A Quadruple 2-Input Positive-NAND Gates datasheet (Rev. U) | PDF | HTML | 2024/7/29 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
開發板
14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組
14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用於支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| VQFN (RGY) | 14 | Ultra Librarian |
| WQFN (BQA) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |