SN74LV6T07
- Wide operating range of 1.65 V to 5.5 V
- 5.5-V tolerant input pins
- LVxT enhanced inputs combined with
open-drain outputs provide maximum voltage translation
flexibility:
- Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
- Up translation from 1.2 V to 5 V with 1.8-V supply
- Down translation from 5 V to 0.8 V or even less with any valid supply
- 5.5-V tolerant input pins
- Supports standard function pinout
- Latch-up performance exceeds 250 mA per JESD 17
The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV6T07 Hex Open-Drain Buffers with Integrated Translation datasheet | PDF | HTML | 2023/8/21 | ||
| 應用說明 | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/7/12 | |||
| 應用說明 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/7/3 | |||
| Application brief | Enabling Modular PLC System Designs with Single-Supply Level Translation | PDF | HTML | 2024/4/16 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (BQA) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |