SN74LV3T99

現行

具有整合式電壓位準轉換器的超級可配置 3 通道多功能閘

產品詳細資料

Operating temperature range (°C) to
Operating temperature range (°C) to
VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 100mAper JESD 17
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 100mAper JESD 17

The SN74LV3T99 device contains three independent configurable logic gates with 3-state outputs. Each gate has four inputs and performs the Boolean function Y = (A • C + B • C) ⊕ D. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer by connecting the inputs A, B, C, and D appropriately.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The SN74LV3T99 device contains three independent configurable logic gates with 3-state outputs. Each gate has four inputs and performs the Boolean function Y = (A • C + B • C) ⊕ D. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer by connecting the inputs A, B, C, and D appropriately.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

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最新 SN74AHCT3G99 現行 具有 3 態輸出的超級可配置多功能 3 通道閘 Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

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* 資料表 SN74LV3T99 Ultra-Configurable Multiple-Function Gates with 3-State Outputs and Logic-Level Shifter datasheet PDF | HTML 2025/11/21

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RKS) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian

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