SN74LV165A
- VCC operation of 2 V to 5.5 V
- Maximum tpd of 10.5 ns at 5 V
- Support mixed-mode voltage operation on all ports
- Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 250 mA per JESD 17
The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCC operation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, Q H.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV165A Parallel-Load 8-Bit Shift Registers datasheet (Rev. R) | PDF | HTML | 2023/3/16 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| TVSOP (DGV) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| VQFN (RGY) | 16 | Ultra Librarian |
| SSOP (DB) | 16 | Ultra Librarian |
| WQFN (BQB) | 16 | Ultra Librarian |